Datasheet

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Block Diagram
SERIAL
MANAGEMENT
MII
TX_CLK
TXD[3:0]
TX_ER TX_EN
MDIO
MDC
COL CRS
RX_ER
RX_DV
RXD[3:0]
RX_CL
MII INTERFACE/CONTROL
RX_EN
TRANSMIT CHANNELS &
100 MB/S 10 MB/S
NRZ TO
MANCHESTER
ENCODER
STATE MACHINES
TRANSMIT
FILTER
LINK PULSE
GENERATOR
4B/5B
ENCODER
SCRAMBLER
PARALLEL TO
SERIAL
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
RECEIVE CHANNELS &
100 MB/S 10 MB/S
MANCHESTER
TO NRZ
DECODER
STATE MACHINES
RECEIVE
FILTER
LINK PULSE
DETECTOR
4B/5B
DECODER
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
MLT-3 TO
10/100 COMMON
AUTO-NEGOTIATION
STATE MACHINE
FAR-END-FAULT
STATE MACHINE
REGISTERS
AUTO
100BASE-X
10BASE-T
MII
NODE/RPTR
PCS CONTROL
PHY ADDRESS
NEGOTIATION
CLOCK
CLOCK
RECOVERY
CLOCK
RECOVERY
CODE GROUP
ALIGNMENT
SMART
SQUELCH
RX_DATA
RX_CLK
RX_DATA
RX_CLK
TX_DATA
TX_DATA
TX_CLK
SYSTEM CLOCK
REFERENCE
FXSD/CD+/−
TPRD+/−TPTD+/−
OUTPUT DRIVER
FXTD/AUITD+/−
INPUT BUFFER
BINARY
DECODER
ADAPTIVE
EQ
AND
BLW
COMP.
FXRD/AUIRD+/−
LED
DRIVERS
LEDS
HARDWARE
CONFIGURATION
PINS
TXAR100
(REPEATER,
SERIAL10, SYMBOL,
AN0, AN1,FXEN
PHYAD[4:0])
,
GENERATION