Datasheet

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3.0 Configuration
This section includes information on the various configura-
tion options available with the DP83843. The configuration
options described herein include:
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs Full Duplex
— 100M Symbol mode
— 100BASE-FX mode
— 10M serial MII mode
— 10M AUI Mode
— Repeater vs. Node
— Isolate mode
— Loopback mode
3.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest per-
formance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signaling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to clause 28 of the IEEE
802.3u specification. The DP83843 supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the high-
est performance protocol will be selected based on the
ability of the Link Partner. The Auto-Negotiation function
within the DP83843 can be controlled either by internal
register access or by use of the AN1 and AN0 (pins 3 & 4).
3.1.1 Auto-Negotiation Pin Control
The state of AN0 and AN1 determines whether the
DP83843 is forced into a specific mode or Auto-Negotiation
will advertise a specific ability (or set of abilities) as given in
Table 3. Pins AN0 and AN1 are implemented as three-level
control pins which are configured by connecting them to
V
CC
, GND, or by leaving them unconnected (refer to
Figure 15). These pins allow configuration options to be
selected without requiring internal register access.
It should be noted that due to the internal resistor networks
depicted in Figure 15, the AN0 or AN1 should be con-
nected directly to either V
CC
or GND, depending on the
requirements. These pins should never be resistively tied to
V
CC
or GND as this will interfere with the internal pull-up
and pull-down resistors resulting in improper Auto-Negotia-
tion behavior.
The state of AN0 and AN1, upon power-up/reset, deter-
mines the state of bit 9 in the PHYSTS register (address
10h) as well as bits [8:5] of the ANAR register (address
04h).
Upon power-up/reset the DP83843 uses default register
values, which enables Auto-Negotiation and advertises the
full set of abilities (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex)
unless subsequent software accesses modify the mode.
The status of Auto-Negotiation as a function of hardware
configuration via the AN0 and AN1 pins is reflected in bit 9
of the PHYSTS register (address 10h).
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 00h.
3.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83843 transmits
the abilities programmed into the Auto-Negotiation Adver-
tisement register (ANAR) at address 04h via FLP Bursts.
Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and
Full Duplex modes may be selected. The default setting of
bits [8:5] in the ANAR and bit 9 in the PHYSTS register
(address 10h) are determined at power-up or hard reset by
the state of the AN0 and AN1 pins.
The BMCR provides software with a mechanism to control
the operation of the DP83843. However, the AN0 and AN1
pins do not affect the contents of the BMCR and cannot be
used by software to obtain status of the mode selected.Bits
1 & 2 of the PHYSTS register (address 10h) are only valid
if Auto-Negotiation is disabled or after Auto-Negotiation is
complete.
The contents of the ANLPAR register are used to automati-
cally configure to the highest performance protocol
between the local and far-end ports. Software can deter-
mine which mode has been configured by Auto-Negotiation
by comparing the contents of the ANAR and ANLPAR reg-
isters and then selecting the technology whose bit is set in
both the ANAR and ANLPAR of highest priority relative to
the following list.
Figure 15. 3 Level Hardware Configuration Pin Control
DECODER
-
+
-
+
R
R
GND
V
L
OUT
A
B
V
IN
V
CC
V
H
V
IN
A B OUT
0V L L L
V
CC
/2 L H M
V
CC
H H H