Datasheet
2.0 Functional Description (Continued)
26 www.national.com
LBR(17h)) and disable Auto-Negotiation. Without FEFI
enabled the DP83843 will not send the FEFI idle pattern.
Additionally, upon detection of Far End Fault, all receive
and transmit MII activity is disabled/ignored (MII serial
management is unaffected).
This function is optional for 100BASE-FX compliance and
should be disabled for 100BASE-TX compliance. If Auto-
Negotiation is enabled (bit 12 of the BMCR) then FEFI is
automatically disabled. FEFI is automatically enabled when
the DP83843 is configured for 100BASE-FX operation.
2.5.3 Software Enable
The FX functions can also be set via software. The FX-
interface is set by bit 5 of the PHYCTRL register (address
19h). The FEFI_EN function is set by bit 14 of register 16h.
The bypass scrambler and de-scrambler function is set by
bit 11 of the loopback and bypass register (address 17h).
2.5.4 FX Interface Considerations
The termination and signal routing for the high-speed
PECL signals are critical. The following diagram shows a
typical thevenin termination circuit.
Chapter 26 of the 802.3u 100BASE-X document includes
references to the three most common types of 125 Mb/s
optical transceiver connectors available. The DP83843 may
be used with any of these three connectors.
It is important to note that the typical 9-pin low cost fiber
transceiver utilizes a single-ended PECL output for Signal
Detect indication. Since the DP83843 incorporates stan-
dard differential PECL inputs for Signal Detect, the FXSD-
input (pin 47) can be externally biased as depicted in
Figure 12 to ensure proper operation.
Optionally, the proper bias potential for FXSD- can be gen-
erated by the DP83843 internally. This is accomplished by
setting bit 15 of register 16 (PCSR). This option eliminates
the requirement for additional external passive components
which would otherwise be required for the proper biasing of
FXSD- in an application where only a single-ended SD sig-
nal is available.
2.6 AUI
The DP83843 is capable of operating in 10BASE-2 and
10BASE-5 applications. This is done by utilizing the AUI
(Attachment Unit Interface) pins of the DP83843. The AUI
interface is completely IEEE 802.3 compliant. See
Figure 14 for an example of a typical AUI connector setup.
AUI mode is selected by bit 5 (AUI_SEL) of the 10BASE-T
Control and Status register (10BTSCR). It can also be acti-
vated by the Autoswitch feature explained below.
Autoswitch overrides the AUI_SEL bit. The Status of the
port, either AUI or TP mode, is displayed in bit 12
(AUI_TPI) of the 10BTSCR register.
2.6.1 AUI Block Diagram
The pins at the AUI interface are AUIRD+/−, AUITD+/−, and
AUICD+/−. They provide the Read, Transmit and Collision
Detect functions respectively. See Figure 13 for a block dia-
gram of the AUI interface. The AUI interface includes the
PLL Decoder, Collision Decoder and Manchester Encoder
and Driver.
The PLL Decoder receives Manchester data from the
transceiver, converts it to NRZ data and clock pulses and
sends it to the controller.
The collision decoder indicates to the MII the presence of a
valid 10 MHz collision signal to the PLL.
Figure 1. Typical DP83843 to Optical Transceiver Interfaces
9-pin Optical Transceiver
DP83843 100BASE-FX
FXRD+/-
FXTD+/-
FXSD+/-
RX_DATA+/-
Signal_Detect +
TX_DATA+/-
V
CC
130Ω
PECL Thevenin Termination
RX
TX
50
43
48
49
47
44
130Ω
130Ω
130Ω
115Ω
115Ω
370Ω
82Ω
82Ω
82Ω 90Ω
90Ω
Figure 1. AUI Block Diagram
PLL
AUIRD+/-
AUICD+/-
AUITD+/-
Decoder
Collision
Decoder
Manchester
Encoder
& Driver
MII Interface/Control
rx_clk
rx_data
crs
col_
detect
tx_data
tx_clk