Datasheet

2.0 Functional Description (Continued)
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2.5.1 FX Interface
When the FX interface is enabled the internal 100BASE-TX
transceiver is disabled. As defined by the 802.3u specifica-
tion, PMD_SIGNAL_indicate (signal detect function),
PMD_UNITDATA.indicate (receive function), and
PMD_UNIT_DATA.request (transmit function) are sup-
ported by the FXSD+/−, FXRD+/−, and FXTD+/− pins
respectively.
Transmit
The DP83843 transmits NRZI data on the FXTD+/− pins.
This data is transmitted at PECL signal levels. 100BASE-
FX requires no scrambling/de-scrambling, so the scrambler
is bypassed in the transmit path. All other PMA and PCS
functions remain unaffected.
Receive
The DP83843 receives NRZI data on the FXRD+/− pins.
This data is accepted at PECL signal levels. 100BASE-FX
requires no scrambling/de-scrambling, so the de-scrambler
is bypassed in the receive path. All other PMA and PCS
functions remain unaffected.
Signal Detect
The DP83843 receives signal detect information on the
FXSD+/− pins. This data is accepted at PECL signal levels.
Signal detect indicates that a signal with the proper ampli-
tude is present at the PMD sublayer.
2.5.2 Far End Fault Indication
Auto-Negotiation provides a mechanism for transferring
information from the Local Station to the Link Partner that a
remote fault has occurred for 100BASE-TX. As Auto-Nego-
tiation is not currently specified for operation over fiber, the
Far End Fault Indication function (FEFI) provides some
degree of communication between link partners in support
of 100BASE-FX operation.
A remote fault is an error in the link that one station can
detect while the other cannot. An example of this is a dis-
connected fiber at a station’s transmitter. This station will
be receiving valid data and detect that the link is good via
the Link Integrity Monitor, but will not be able to detect that
its transmission is not propagating to the other station.
A 100BASE-FX station that detects such a remote fault
(through the deassertion of signal detect) may modify its
transmitted IDLE stream from all ones to a group of 84
ones followed by a single zero (i.e. 16 IDLE code groups
followed by a single Data 0 code group). This is referred to
as the FEFI IDLE pattern. Transmission of the FEFI IDLE
pattern will continue until FXSD+/− is re-asserted.
If three or more FEFI IDLE patterns are detected by the
DP83843, then bit 4 of the Basic Mode Status register
(address 01h) is set to one until read by management. It is
also set in bit 7 of the PHY Status register (address 10h).
The first FEFI IDLE pattern may contain more than 84 ones
as the pattern may have started during a normal IDLE
transmission which is actually quite likely. However, since
FEFI is a repeating pattern, this will not cause a problem
with the FEFI function. It should be noted receipt of the
FEFI IDLE pattern will not cause CRS to assert.
To enable Fiber mode without FEFI, set bits 9:7 of the LBR
register to <011>, disable FEFI (bit 14 of register
PCSR(16h)), bypass the scrambler (bit 12 of register
Figure 1. 100Base-FX Block Diagram
NRZ TO NRZI
ENCODER
BINARY
TO MLT-3 /
COMMON
DRIVER
PECL
DRIVER
FXTD
TPRD+/−
INPUT &BLW COMP
FULL ADAPT. EQUALIZ.
MLT-3 TO BINARY DEC.
SIGNAL
DETECT
CLOCK
RECOVERY
MODULE
PECL
INPUTS
FXSDFXRD
NORMAL TX DATA
W/ SCRAMBLER BYPASSED
NORMAL RX DATA TO
DESCRAMBLER BYPASS
NORMAL
SIGNAL DETECT
TPTD+/−