Datasheet

2.0 Functional Description (Continued)
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packets with inverted End-of-Packet pulses are received,
bad polarity is reported.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
The bad polarity condition is latched and the LED_ FDPOL
output is asserted. The DP83843's 10BASE-T transceiver
module corrects for this error internally and will continue to
decode received data correctly. This eliminates the need to
correct the wiring error immediately.
2.4.9 10BASE-T Internal Loopback
When the 10MB_ENDEC_LB bit in the LBR (bit 4, register
address 17h) is set, 10BASE-T transmit data is looped
back in the ENDEC to the receive channel. The transmit
drivers and receive input circuitry are disabled in trans-
ceiver loopback mode, isolating the transceiver from the
network.
Loopback is used for diagnostic testing of the data path
through the transceiver without transmitting on the network
or being interrupted by receive traffic. This loopback func-
tion causes the data to loopback just prior to the 10BASE-T
output driver buffers such that the entire transceiver path is
tested.
2.4.10 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83843 as the required signal conditioning is integrated.
Only isolation/step-up transformers and impedance match-
ing resistors are required for the 10BASE-T transmit and
receive interface. The internal transmit filtering ensures
that all the harmonics in the transmit signal are attenuated
by at least 30 dB.
2.4.11 Encoder/Decoder (ENDEC) Module
The ENDEC module consists of essentially four functions:
The oscillator generates the 10 MHz transmit clock signal
for system timing from an external 25 MHz oscillator.
The Manchester encoder accepts NRZ data from the con-
troller or repeater, encodes the data to Manchester, and
transmits it differentially to the transceiver, through the dif-
ferential transmit driver.
The Manchester decoder receives Manchester data from
the transceiver, converts it to NRZ data and recovers clock
pulses for synchronous data transfer to the controller or
repeater.
The collision monitor indicates to the controller the pres-
ence of a valid 10 Mb/s collision signal.
2.4.12 Manchester Encoder
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts the NRZ data to
pre-emphasized Manchester data for the transceiver. For
the duration of TX_EN remaining high, the Transmit Data
(TPTD+/−) is encoded for the transmit-driver pair
(TPTD+/−). TXD must be valid on the rising edge of Trans-
mit Clock (TX_CLK). Transmission ends when TX_EN
deasserts. The last transition is always positive; it occurs at
the center of the bit cell if the last bit is a one, or at the end
of the bit cell if the last bit is a zero.
2.4.13 Manchester Decoder
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be exter-
nally terminated with either a differential 100ohm termina-
tion network to accommodate UTP cable.
The decoder detects the end of a frame when no more mid-
bit transitions are detected. Within one and a half bit times
after the last bit, carrier sense is de-asserted. Receive
clock stays active for five more bit times after CRS goes
low, to guarantee the receive timings of the controller or
repeater.
2.5 100 BASE-FX
The DP83843 is fully capable of supporting 100BASE-FX
applications. 100BASE-FX is similar to 100BASE-TX with
the exceptions being the PMD sublayer, lack of data scram-
bling, and signaling medium and connectors. Chapter 26 of
the IEEE 802.3u specification defines the interface to this
PMD sublayer.
The DP83843 can be configured for 100BASE-FX opera-
tion either through hardware or software. Configuration
through hardware is accomplished by forcing the
FXEN pin
(pin 21) to a logic low level prior to power-up/reset. Config-
uration through software is accomplished by setting bits 9:7
of the LBR register to <011>, enabling FEFI (bit 14 of regis-
ter PCSR(16h)), bypassing the scrambler (bit 12 of register
LBR(17h)) and disabling Auto-Negotiation. In addition, set-
ting the FX_EN bit of the PHYCTRL register (bit 5, address
19h) accomplishes the same function as forcing the
FXEN
pin (pin 21) to a logic low. In 100BASE-FX mode, the FX
interface is enabled along with the Far End Fault Indication
(FEFI) and Bypass Scrambler functions. Auto-Negotiation
must be disabled in order for 100BASE-FX operation to
work properly.
The diagram in Figure 11 is a block diagram representation
of the FX interface and the alternative data paths for trans-
mit, receive and signal detect.