Datasheet

2.0 Functional Description (Continued)
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the MAC preamble. Specifically, the J/K 10-bit code-group
pair is replaced by the nibble pair (0101 0101). All subse-
quent 5B code-groups are converted to the corresponding
4B nibbles for the duration of the entire packet. This con-
version ceases upon the detection of the T/R code-group
pair denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
2.3.11 100BASE-X Link Integrity Monitor
The 100BASE-X Link Integrity Monitor function (LIM)
allows the receiver to ensure that reliable data is being
received. Without reliable data reception, the LIM will halt
both transmit and receive operations until such time that a
valid link is detected (i.e. good link).
If Auto-Negotiation is not enabled, then a valid link will be
indicated once SD+/− is asserted continuously for 500 µs.
If Auto-Negotiation is enabled, then Auto-Negotiation will
further qualify a valid link as follows:
— The descrambler must receive a minimum of 12 IDLE
code groups for proper link initialization.
— The Auto-Negotiation must determine that the
100BASE-X function should be enabled.
A valid link for a non-Auto-Negotiating application is indi-
cated by either the Link LED output or by reading bit 2 of
the Basic Mode Status Register BMSR (address 01h). For
a truly qualified valid link indication as a result of Auto-
Negotiation, bit 2 of the BMSR register (address 01h) must
be read.
2.3.12 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83843 will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups. In
order to exit this state the PHYTER must receive at least
two IDLE code groups and the PHYTER cannot receive a
single IDLE code group at any time. In addition, the False
Carrier Event Counter (address 14h) will be incremented
by one. Once the PHYTER exits this state, RX_ER and
CRS become de-asserted.
When bit 11 of the LBR register is one (BP_RX), RXD[3:0]
and RX_ER/RXD[4] are not modified.
2.3.13 Carrier Integrity Monitor
The Carrier Integrity Monitor function (CIM) protects the
repeater from transient conditions that would otherwise
cause spurious transmission due to a faulty link. This func-
tion is required for repeater applications and is not speci-
fied for node applications.
The REPEATER pin (pin 63) determines the default state of
bit 5 of the PCS register (Carrier Integrity Monitor Disable,
address 16h) to automatically enable or disable the CIM
function as required for IEEE 802.3 compliant applications.
After power-up/reset, software may enable or disable this
function independent of Repeater or Node mode.
If the CIM determines that the link is unstable, the
DP83843 will not propagate the received data or control
signaling to the MII and will ignore data transmitted via the
MII. The DP83843 will continue to monitor the receive
stream for valid carrier events.
Detection of an unstable link condition will cause bit 4 of
the PCS register (address 16h) to be set to one. This bit is
cleared to zero upon a read operation once a stable link
condition is detected by the CIM. Upon detection of a sta-
ble link, the DP83843 will resume normal operations.
The Disconnect Counter (address 13h) increments each
time the CIM determines that the link is unstable.
2.4 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compli-
ant. It includes the receiver, transmitter, collision, heart-
beat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83843. Due to the complexity and scope of the
10BASE-T Transceiver block and various sub-blocks, this
section focuses on the general system level operation.
2.4.1 Operational Modes
The DP83843 has 2 basic 10BASE-T operational modes:
Half Duplex mode
Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83843 functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83843 is capable of simulta-
neously transmitting and receiving without asserting the
collision signal. The DP83843's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
2.4.2 Oscillator Module Operation
A 25 MHz crystal or can-oscillator with the following specifi-
cations is recommended for driving the X1 input.
1. CMOS output with a 50ppm frequency tolerance.
2. 35-65% duty cycle (max).
3. Two TTL load output drive.
Additional output drive may be necessary if the oscillator
must also drive other components. When using a clock
oscillator it is still recommended that the designer connect
the oscillator output to the X1 pin and leave X2 floating.
2.4.3 Smart Squelch
The smart squelch is responsible for determining when
valid data is present on the differential receive inputs
(TPRD+/−). The DP83843 implements an intelligent
receive squelch to ensure that impulse noise on the receive
inputs will not be mistaken for a valid signal. Smart squelch
operation is independent of the 10BASE-T operational
mode.
The squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE 802.3
10BASE-T standard) to determine the validity of data on
the twisted pair inputs (refer to Figure 10).
The signal at the start of packet is checked by the smart
squelch and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will
be rejected. Once this first squelch level is overcome cor-
rectly, the opposite squelch level must then be exceeded
within 150 ns. Finally the signal must exceed the original
squelch level within a further 150 ns to ensure that the