Datasheet

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2.0 Functional Description
2.1 802.3u MII
The DP83843 incorporates the Media Independent Inter-
face (MII) as specified in clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a 10/100 Mb/s MAC or a 100 Mb/s repeater con-
troller. This section describes both the serial MII manage-
ment interface as well as the nibble wide MII data interface.
The management interface of the MII allows the configura-
tion and control of multiple PHY devices, the gathering of
status and error information, and the determination of the
type and abilities of the attached PHY(s).
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC
or repeater).
The DP83843 supports the TI ThunderLAN® MII interrupt
function. For further information please contact your local
National sales representative.
2.1.1 Serial Management Register Access
The serial MII specification defines a set of thirty-two 16-bit
status and control registers that are accessible through the
serial management data interface pins MDC and MDIO.
The DP83843 implements all the required MII registers as
well as several optional registers. These registers are fully
described in Section 7. A description of the serial manage-
ment access protocol follows.
2.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 2.5 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for-
mat is shown in Table 1.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order
to initialize the MDIO interface, the Station Management
Entity (SME) sends a sequence of 32 contiguous logic
ones on MDIO to provide the DP83843 with a sequence
that can be used to establish synchronization. This pream-
ble may be generated either by driving MDIO high for 32
consecutive MDC clock cycles, or by simply allowing the
MDIO pull-up resistor to pull the MDIO pin high during
which time 32 MDC clock cycles are provided. In addition
32 MDC clock cycles should be used if an invalid start, op
code, or turnaround bit is detected.
The DP83843 waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83843 serial management port has initialized
no further preamble sequencing is required until after a
power-on/reset has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is an idle bit time inserted between the Regis-
ter Address field and the Data field. To avoid contention, no
device actively drives the MDIO signal during the first bit of
Turnaround during a read transaction. The addressed
DP83843 drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 2
shows the timing relationship between MDC and the MDIO
as driven/received by the Station Management Entity and
the DP83843 (PHY) for a typical register read access.
Table 1. Typical MDIO Frame Format
MII Management
Serial Protocol
<idle><start><op code><device addr> <reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA> <RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA> <RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Figure 1. Typical MDC/MDIO Write Operation
Figure 2. Typical MDC/MDIO Read Operation
MDC
MDIO
00011110000000
(SME)
Idle Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
0 0 0 000 00000000
Z
Idle
1000
ZZ
MDC
MDIO
00011 110000000
(SME)
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
MDIO
(PHY)
Z
Z
Z
0 0 011000100000000
Z
Idle
Z
Z