Datasheet

1.0 Pin Descriptions (Continued)
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1.5 LED Interface
These outputs can be used to drive LEDs directly, or can
be used to provide status information to a network man-
agement device. Refer to section 2.2 for a description of
how to generate LED indication of 100 Mb/s mode. The
active state of each LED output driver is dependent on the
logic level sampled by the corresponding PHY address
input upon power-up/reset. For example, if a given PHYAD
input is resistively pulled low then the corresponding LED
output will be configured as an active high driver. Con-
versely, if a given PHYAD input is resistively pulled high
then the corresponding LED output will be configured as an
active low driver (refer to section 5.0.1 for further details).
Note that these outputs are standard CMOS voltage
drivers and not open-drain.
Signal Name Type Pin # Description
LED_COL
(PHYAD[0])
I/O 42 COLLISION LED: Indicates the presence of collision activity for 10 Mb/s and 100
Mb/s Half Duplex operation. This LED has no meaning for 10 Mb/s or 100 Mb/s Full
Duplex operation and will remain deasserted. During 10 Mb/s half duplex mode this
pin will be asserted after data transmission due to the heartbeat function.
The DP83843 incorporates a “monostable” function on the LED_COL output. This
ensures that even collisions generate adequate LED ON time (approximately 50
ms) for visibility.
LED_TX
(PHYAD[1])
I/O 41 TRANSMIT LED: Indicates the presence of transmit activity for 10 Mb/s and 100
Mb/s operation.
If bit 7 (LED_Trans_MODE) of the PHYCTRL register (address 19h) is set high,
then the LED_TX pin function is changed to indicate the status of the Disconnect
function as defined by the state of bit 4 (CIM_STATUS) in the 100 Mb/s PCS con-
figuration & status register (address 16h). See register definition for complete de-
scription of alternative operation.
The DP83843 incorporates a “monostable” function on the LED_TX output. This en-
sures that even minimum size packets generate adequate LED ON time (approxi-
mately 50 ms) for visibility.
LED_RX
(PHYAD[2])
I/O 40 RECEIVE LED: Indicates the presence of any receive activity for 10 Mb/s and 100
Mb/s operation. See register definitions(PHYCTRL register and PCSR register) for
complete descriptions of alternative operation.
The DP83843 incorporates a “monostable” function on the LED_RX output. This en-
sures that even minimum size packets generate adequate LED active time (approx-
imately 50 ms) for visibility.
LED_LINK
(PHYAD[3])
I/O 39 LINK LED: Indicates good link status for 10 Mb/s and 100 Mb/s operation.
In 100BASE-T mode, link is established as a result of input receive amplitude com-
pliant with TP-PMD specifications which will result in internal generation of Signal
Detect as well as an internal signal from the Clock Recovery Module (cypher &
sync). LED_LINK will assert after these internal signals have remained asserted for
a minimum of 500µs. Once Link is established, then cipher & sync are no longer
sampled and the Link will remain valid as long as Signal Detect is valid. LED_LINK
will deassert immediately following the deassertion of the internal Signal Detect.
10 Mb/s link is established as a result of the reception of at least seven consecutive
normal Link Pulses or the reception of a valid 10BASE-T packet which will cause
the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link
Loss Timer as specified in IEEE 802.3.
In 100BASE-FX mode, link is established as a result of the assertion of the Signal
detect input to the DP83843. LED_LINK will assert after Signal Detect has remained
asserted for a minimum of 500µS. LED_LINK will deassert immediately following
the deassertion of signal detect.
The link function is disabled during AUI operation and LED_LINK is asserted.
LED_FDPOL
(PHYAD[4])
I/O 38 FULL DUPLEX LED: Indicates Full Duplex mode status for 10 Mb/s or 100 Mb/s
operation. This pin can be configured to indicate Polarity status for 10 Mb/s opera-
tion. If bit 6 (LED_DUP_MODE) in the PHYCTRL Register (address 19h) is deas-
serted, the LED_FDPOL pin function is changed to indicate Polarity status for 10
Mb/s operation.
The DP83843 automatically compensates for 10BASE-T polarity inversion.
10BASE-T polarity inversion is indicated by the assertion of LED_FDPOL.
SPEED10 O 5 SPEED 10 Mb/s: Indicates 10 Mb/s operation when high. Indicates 100 Mb/s oper-
ation when low. This pin can be used to drive peripheral circuitry such as an LED
indicator.