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DP83843

DP83843 PHYTER

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Summary of content (89 pages)

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DP83843 DP83843 PHYTER /LWHUDWXUH 1XPEHU 61/6 %
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DP83843BVJE PHYTER General Description Features The DP83843BVJE is a full feature Physical Layer device — IEEE 802.3 ENDEC with AUI/10BASE-T transceivers with integrated PMD sublayers to support both 10BASE-T and built-in filters and 100BASE-X Ethernet protocols. — IEEE 802.3u 100BASE-TX compatible - directly drives standard Category 5 UTP, no need for external This VLSI device is designed for easy implementation of 100BASE-TX transceiver 10/100 Mb/s Ethernet LANs.
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Block Diagram MII HARDWARE CONFIGURATION PINS RX_CL RXD[3:0] RX_DV RX_ER RX_EN CRS COL MDC MDIO TX_EN TX_ER (REPEATER, SERIAL10, SYMBOL, , AN0, AN1,FXEN PHYAD[4:0]) TXD[3:0] TX_CLK SERIAL MANAGEMENT MII INTERFACE/CONTROL RX_DATA RX_CLK TX_DATA TX_DATA 4B/5B ENCODER SCRAMBLER REGISTERS MII 10 MB/S PHY ADDRESS NRZ TO MANCHESTER ENCODER AUTO NEGOTIATION PARALLEL TO SERIAL LINK PULSE GENERATOR NRZ TO NRZI ENCODER BINARY TO MLT-3 ENCODER RX_CLK TX_CLK TRANSMIT CHANNELS & STATE MACHINES
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Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Device Configuration Interface . . . . . . . . . . . . . . . 8 1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.
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LED_TX/PHYAD[1] LED_COL/PHYAD[0] FXTD-/AUITD- FXTD+/AUITD+ AUIFX_GND FXSD-/CD- AUIFX_VDD FXSD+/CD+ FXRD-/AUIRD- CP_AGND FXRD+/AUIRD+ CP_AVDD CPTW_DVSS NC CPTW_DVDD NC ATP_GND NC NC TWREF Connection Diagram BGREF 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 NC 62 39 THIN/REPEATER 63 38 LED_FDPOL/PHYAD[4] TW_AGND 64 37 IO_VSS5 TPRD- 65 36 IO_VDD5 VCM_CAP 66 35 MDC MDIO TX_CLK LED_RX/PHYAD[2] LED_LINK/PHYAD[3] TPRD+ 67 34 TW_AVDD 68 33 SERI
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1.0 Pin Descriptions The DP83843 pins are classified into the following interface — DEVICE CONFIGURATION INTERFACE categories. Each interface is described in the sections that — LED INTERFACE follow. — PHY ADDRESS INTERFACE — MII INTERFACE — RESET — 10/100 Mb/s PMD INTERFACE — POWER AND GROUND PINS — CLOCK INTERFACE — SPECIAL CONNECT PINS 1.
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1.0 Pin Descriptions (Continued) Signal Name Type RXD[3] O, Z Pin # 12 RXD[2] 13 RXD[1] 14 RXD[0] 15 Description RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK, 25 MHz for 100BASE-X mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK. In 10 Mb/s serial mode, the RXD[0] pin is used as the data output pin which is also clocked out on the falling edge of RX_CLK. During 10 Mb/s serial mode RXD[3:1] pins become don't cares.
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1.0 Pin Descriptions (Continued) Signal Name Type Pin # FXRD-/AUIRD- I 49 FXRD+/AUIRD+ (PECL 50 or Description 100BASE-FX or 10 Mb/s AUI RECEIVE DATA: This configurable input buffer supports either 125 Mb/s PECL, for 100BASE-FX applications, or 10 Mb/s AUI signaling. When configured as a 100BASE-FX receiver this input accepts 100BASE-FX standard compliant binary data direct from an optical transceiver.
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1.0 Pin Descriptions (Continued) 1.3 Clock Interface Signal Name Type Pin # Description X1 I 9 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83843 and must be connected to a 25 MHz 0.005% (50 ppm) clock source. The DP83843 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
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1.0 Pin Descriptions (Continued) Signal Name REPEATER Type I/O Pin # 63 (THIN) Description REPEATER/NODE MODE: Selects 100 Mb/s Repeater mode when set high and node mode when set low. When set in Repeater mode the DP83843 only supports 100 Mb/s data rates. In Repeater mode (or Node mode with Full Duplex configured), the Carrier Sense (CRS) output from the DP83843 is asserted due to receive activity only. In Half Duplex Node mode, CRS is asserted due to either receive or transmit activity.
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1.0 Pin Descriptions (Continued) 1.5 LED Interface These outputs can be used to drive LEDs directly, or can be used to provide status information to a network management device. Refer to section 2.2 for a description of how to generate LED indication of 100 Mb/s mode. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon power-up/reset.
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1.0 Pin Descriptions (Continued) 1.6 PHY Address Interface The DP83843 PHYAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros Signal Name Type PHYAD[0] (00000) will result in a PHY isolation condition as a result of power-on/reset, as specified in IEEE 802.3u. Pin # I/O 42 (LED_COL) Description PHY ADDRESS [0]: PHY address sensing pin for multiple PHY applications.
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1.0 Pin Descriptions (Continued) 1.8 Power And Ground Pins supply pairs. This grouping allows for optimizing the layout and filtering of the power and ground supplies to this The power (VCC) and ground (GND) pins of the DP83843 device.
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2.0 Functional Description 2.1 802.3u MII The DP83843 incorporates the Media Independent Interface (MII) as specified in clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a 10/100 Mb/s MAC or a 100 Mb/s repeater controller. This section describes both the serial MII management interface as well as the nibble wide MII data interface.
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2.0 Functional Description (Continued) For write transactions, the Station Management Entity writes data to an addressed DP83843 eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity inserting <10> for these two bits. Figure 1 shows the timing relationship for a typical MII register write access. 2.1.3 Preamble Suppression The DP83843 supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h).
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2.0 Functional Description (Continued) 2.2 100BASE-TX TRANSMITTER The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, TPTD+/−, can be directly routed to the AC coupling magnetics. The block diagram in Figure 3 provides an overview of each functional block within the 100BASE-TX transmit section.
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2.0 Functional Description (Continued) The code-group encoder converts 4 bit (4B) nibble data generated by the MAC into 5 bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 2 for 4B to 5B code-group mapping details. 2.2.1 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications).
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2.0 Functional Description (Continued) Table 2.
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2.0 Functional Description (Continued) The 100BASE-TX MLT-3 signal sourced by the TPTD+/− common driver output pins is slow rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD compliant transition times (3 ns < Tr < 5ns). The 100BASE-TX transmit TP-PMD function within the DP83843 is capable of sourcing only MLT-3 encoded data. Binary output from the TPTD+/− outputs is not possible in 100 Mb/s mode. 2.2.
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2.0 Functional Description (Continued) RX_CLK RXD[3:0] / RX_ER BP_RX MUX BP_4B5B MUX CARRIER INTEGRITY MONITOR SD 4B/5B DECODER LINK INTEGRITY MONITOR CODE GROUP ALIGNMENT RX_DATA VALID SSD DETECT MUX BP_SCR DESCRAMBLER SERIAL TO PARALLEL CLOCK DATA NRZI TO NRZ DECODER CLOCK RECOVERY MODULE MLT-3 TO BINARY DECODER DIGITAL ADAPTIVE EQUALIZATION INPUT &BLW COMPENSATION SIGNAL DETECT TPRD +/− Figure 1. Receive Block Diagram 19 www.national.
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2.0 Functional Description (Continued) attenuation caused by frequency variations must be compensated for to ensure the integrity of the transmission. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths.
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2.0 Functional Description (Continued) required function for ultimately providing data to the nibblewide interface of the MII. 2.3.8 Descrambler A 5-bit parallel (code-group wide) descrambler is used to descramble the receive NRZ data.
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2.0 Functional Description (Continued) the MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
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2.0 Functional Description (Continued) Twisted Pair Squelch Operation <150ns <150ns >150ns Vsq + Vsq + reduced Vsq reduced Vsq start of packet end of packet Figure 1. 10BASE-T Twisted Pair Smart Squelch Operation input waveform will not be rejected. The checking proce- 2.4.5 Normal Link Pulse Detection/Generation dure results in the loss of typically three preamble bits at The link pulse generator produces pulses as defined in the the beginning of each packet. IEEE 802.3 10BASE-T standard.
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2.0 Functional Description (Continued) packets with inverted End-of-Packet pulses are received, 2.4.12 Manchester Encoder bad polarity is reported. The encoder begins operation when the Transmit Enable A polarity reversal can be caused by a wiring error at either input (TX_EN) goes high and converts the NRZ data to end of the cable, usually at the Main Distribution Frame pre-emphasized Manchester data for the transceiver. For (MDF) or patch panel in the wiring closet.
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2.0 Functional Description (Continued) NORMAL RX DATA TO DESCRAMBLER BYPASS NORMAL TX DATA W/ SCRAMBLER BYPASSED NORMAL SIGNAL DETECT CLOCK RECOVERY MODULE NRZ TO NRZI ENCODER PECL INPUTS PECL DRIVER SIGNAL DETECT INPUT &BLW COMP BINARY TO MLT-3 / COMMON DRIVER FULL ADAPT. EQUALIZ. MLT-3 TO BINARY DEC. TPTD+/− FXTD FXRD FXSD TPRD+/− Figure 1.
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2.0 Functional Description (Continued) LBR(17h)) and disable Auto-Negotiation. Without FEFI This function is optional for 100BASE-FX compliance and enabled the DP83843 will not send the FEFI idle pattern. should be disabled for 100BASE-TX compliance. If AutoAdditionally, upon detection of Far End Fault, all receive Negotiation is enabled (bit 12 of the BMCR) then FEFI is and transmit MII activity is disabled/ignored (MII serial automatically disabled.
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2.0 Functional Description (Continued) The Manchester encoder accepts NRZ data from the MII, encodes the data to Manchester and sends it to the driver. The driver transmits the data differentially to the transceiver. 2.6.2 AUI/TP Autoswitch The DP83843 has an autoswitching feature that allows switching between the AUI and TP operation. The AUI/TPI autoswitch feature (AUTOSW_EN) is enabled by bit 9 of the 10BASE-T Control and Status Register (10BTSCR).
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3.0 Configuration This section includes information on the various configura- Figure 15). These pins allow configuration options to be tion options available with the DP83843. The configuration selected without requiring internal register access. options described herein include: It should be noted that due to the internal resistor networks depicted in Figure 15, the AN0 or AN1 should be con— Auto-Negotiation nected directly to either VCC or GND, depending on the — PHY Address and LEDs requirements.
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3.0 Configuration (Continued) Table 3.
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3.0 Configuration (Continued) base and next pages. Software must be available to perform several functions. The ANER (register 6) must have a page received (bit 1), once the DP83843 receives the first page, software must store it in memory if it wants to keep the information. Auto-Negotiation keeps a copy of the base page information but it is no longer accessible by software.
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3.0 Configuration (Continued) that while an address selection of all zeros <00000> will The adaptive nature of the LED outputs helps to simplify result in PHY Isolate mode, this will not effect serial man- potential implementation issues of these dual purpose pins. agement access. Refer to the PHYCTRL register (address 19h) bits [8:6] for further information regarding LED operations and configuration.
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3.0 Configuration (Continued) It is important to understand that while full Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to support full-duplex, parallel detection can not recognize the difference between full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. Therefore, as specified in 802.
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3.0 Configuration (Continued) 3.8 Repeater vs. Node The DP83843 Carrier Sense (CRS) operation depends on the value of the Repeater bit in the PHYCTRL register (bit 9, address 19h). When set high, the CRS output (pin 22) is asserted for receive activity only. When set low, the CRS output is asserted for either receive or transmit activity. The default value for this bit is set by the THIN/REPEATER pin (pin 63) at power-up/reset.
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4.0 Clock Architecture serves to clock out the 125Mb/s serial bit stream for 100BASE-TX and 100BASE-FX applications. The 125 MHz clock is also routed to a counter where it is divided by 5 to produce the 25 MHz TX_CLK signal for the transmit MII.
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4.0 Clock Architecture (Continued) 125Mb/s Serial Data Input Phase Detector Phase Error Processor Deserializer RXD [4:0] Digital Loop Filter 25 MHz RX_CLK Divide by 2 Phase to Frequency Converter Frequency Reference From CGM Frequency Controlled Oscillator Figure 18.
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4.0 Clock Architecture (Continued) 4.2 100BASE-X Clock Recovery Module The diagram in Figure 18 illustrates a high level block architecture of the 100BASE-X Clock Recovery circuit. The 125Mb/s serial binary receive data stream that has been recovered by the integrated TP-PMD receiver is routed to the input of the phase detector.
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5.0 Reset Operation Table 4. Latched pins at Reset The DP83843 can be reset either by hardware or software. A hardware reset may be accomplished either by asserting the RESET pin during normal operation, or upon powering up the device. A software reset is accomplished by setting the reset bit in the Basic Mode Control Register. Pin # While either the hardware or software reset can be implemented at any time after device initialization, providing a hardware reset, as described in Section 6.
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6.0 DP83843 Application 6.1 Typical Node Application 6.2 Power And Ground Filtering Figure 22 illustrates a typical implementation of a 10/100 Mb/s node application. This is given only to indicate the major circuit elements of such a design. It is not intended to be a full circuit diagram. For detailed system level application information please contact your local National sales representative.
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6.0 DP83843 Application (Continued) system design, empirical data has shown a resultant improvement (reduction) in radiated emissions testing. Additionally, by eliminating power plane partitioning within the system VCC and system ground domains, specific impedance controlled signal routing can remain uninterrupted.
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6.0 DP83843 Application (Continued) Chassis Ground Layer 1 (top) Ground Plane: Chassis Signal Routing Magnetics DP83843 RJ45 System Ground Layer 2 Signal Routing Ground Plane: System Ground DP83843 Magnetics RJ45 System Ground Layer 3 System VCC VCC Signal Routing Planes: DP83843 Magnetics RJ45 System VCC System VCC Chassis Ground Layer 4 (bottom) Ground Plane: Signal Routing DP83843 Magnetics RJ45 Chassis Figure 24. Typical plane layout recommendation for DP83843 40 www.
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6.0 DP83843 Application (Continued) For applications where high reliability is required, it is recommended that additional ESD protection diodes be added as shown below. There are numerous dual series connected diode pairs that are available specifically for ESD protection. The level of protection will vary dependent upon the diode ratings. The primary parameter that affects the level of ESD protection is peak forward surge current.
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7.0 User Information 7.1 Link LED While in Force 100Mb/s Good Link not complete the negotiation since it is not advertising 100Mb/s capability. In an application in which the user only desires 10Mb/s operation and is being sent 100Mb/s signals, then the correct operation is to never complete the negotiation. Type: Information Hardware Problem: The Good Link LED (LED_LINK pin 39) will not assert when the DP83843BVJE is programmed to force good link in 100Mb/s mode.
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resistor be placed between the TWREF pin (pin 60) and Description: TW_AGND. (1/10th Watt resistor with a 1% tolerance is The Next Page Toggle bit is used only in Next Page operarecommended) tions, and is used to distinguish one page from another. The AutoNegotiation specification indicates that the toggle 7.5 Magnetics bit should take on an initial value equal to that of bit 11 in Type: the ANAR, Reg 4h.
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Description: 7.10 BAD_SSD Event Lockup The symptoms of this problem include: Type: Register 1: Will show negotiation NOT complete (bit 5 = 0) Urgent Hardware Register 6: Will show a page received, then page receive Problem: will be cleared on read of this register (bit 1 = 1, then bit 1 = When the PHYTER receives a particular invalid data 0 if read twice) sequence, it can get stuck in the RX_DATA state with an Register 1a: Will have the data 00a3 invalid alignment.
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8.0 Register Block 8.1 Register Definitions Register maps and address definitions are given in the following tables: Table 5.
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8.0 Register Block (Continued) Table 6. Basic Mode Control Register (BMCR) Address 00h Bit 15 Bit Name Reset Default 0, RW/SC Description Reset: 1 = Initiate software Reset / Reset in Process 0 = Normal operation This bit sets the status and control registers of the PHY to their default states. This self-clearing bit returns a value of one until the reset process is complete (approximately 1.2 ms for reset duration).
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8.0 Register Block (Continued) Table 6. Basic Mode Control Register (BMCR) Address 00h (Continued) Bit 10 Bit Name Isolate Default Strap, RW Description Isolate: 1 = Isolates the DP83843 from the MII with the exception of the serial management. When this bit is asserted, the DP83843 does not respond to TXD[3:0], TX_EN, and TX_ER inputs, and it presents a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS outputs.
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8.0 Register Block (Continued) Table 7.
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8.0 Register Block (Continued) The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83843. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. Table 8.
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8.0 Register Block (Continued) Table 10. Auto-Negotiation Advertisement Register (ANAR) Address 04h (Continued) Bit 7 Bit Name TX Default Strap, RW Description 100BASE-TX Support: 1 = 100BASE-TX is supported by the local device 0 = 100BASE-TX not supported At reset, this bit is set by AN0/AN1. After reset, this bit may be written to by software.
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8.0 Register Block (Continued) Table 11.
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8.0 Register Block (Continued) Table 11. Auto-Negotiation Link Partner Ability Register (ANLPAR) Address 05h Bit Bit Name Default Description This register also contains the Link Partner Next Page contents.
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8.0 Register Block (Continued) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 13.
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8.0 Register Block (Continued) This register provides a single location within the register set for quick access to commonly accessed information. Table 14.
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8.0 Register Block (Continued) Table 14. PHY Status Register (PHYSTS) Address 10h (Continued) Bit 3 Bit Name Loopback Status Default 0, RO Description Loopback: 1 = Loopback enabled 0 = Normal operation 2 Duplex Status RO Duplex: This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.
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8.0 Register Block (Continued) This counter provides information required to implement the isolates attribute within the Repeater Port managed object class of Clause 30 of the IEEE 802.3 specification. Table 17. Disconnect Counter Register (DCR) Address 13h Bit 15:0 Bit Name DCNT[15:0] Default <0000h>, RW / COR Description Disconnect Counter: This 16 bit counter increments for each isolate event.
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8.0 Register Block (Continued) Table 20. 100 Mb/s PCS Configuration and Status Register (PCSR) Address 16h (Continued) Bit 12 Bit Name DESCR_TO_SEL Default 0, RW Description Descrambler Time-out Select: 1 = Descrambler Timer set to 2 ms 0 = Descrambler Timer set to 722 µs The Descrambler Timer selects the interval over which a minimum number of IDLES are required to be received to maintain descrambler synchronization. The default time of 722 µs supports 100BASE-X compliant applications.
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8.0 Register Block (Continued) Table 20. 100 Mb/s PCS Configuration and Status Register (PCSR) Address 16h (Continued) Bit 4 Bit Name CIM_STATUS Default 0, RO Description Carrier Integrity Monitor Status: This bit indicates the status of the Carrier Integrity Monitor function. This status is optionally muxed out through the TX_LED pin when the LED_TXRX_MODE bits (8:7) of the PHYCTRL register (address 19h) are set to either <10> or <01>.
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8.0 Register Block (Continued) Table 21. Loopback & Bypass Register (LBR) Address 17h (Continued) Bit 12 Bit Name BP_SCR Default Strap, RW Description Bypass Scrambler/Descrambler Function: This bit is set according to the strap configuration of the SYMBOL pin or the FXEN pin at power-up/reset. After reset this bit may be written to by software.
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8.0 Register Block (Continued) Table 21. Loopback & Bypass Register (LBR) Address 17h (Continued) Bit Bit Name Default Description 1 RESERVED 0, RO Reserved: Writes as 0, read as 0 0 RESERVED 0, RO Reserved: Writes as 0, read as 0 Table 22.
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8.0 Register Block (Continued) Table 22. 10BASE-T Control & Status Register (10BTSCR) Address 18h (Continued) Bit 6 Bit Name Default LS_SEL 0, RW Description Low Squelch Select: Selects between standard 10BASE-T receiver squelch threshold and a reduced squelch threshold that is useful for longer cable applications.
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8.0 Register Block (Continued) Table 23. PHY Control Register (PHYCTRL) Address 19h (Continued) Bit 9 Bit Name REPEATER Default Strap, RW Description Repeater/Node Mode: 1 = Repeater mode 0 = Node mode In repeater mode the Carrier Sense (CRS) output from the device is asserted due to receive activity only. In Node mode, and not configured for full duplex operation, CRS is asserted due to either receive or transmit activity. In 100 Mb/s operation the CIM monitor is disabled.
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9.0 Electrical Specifications Absolute Maximum Ratings Supply Voltage (VCC) Recommended Operating Conditions -0.5 V to 7.0 V Input Voltage (DCIN) -0.5 V to VCC + 0.5 V Supply voltage (VDD) Output Voltage (DCOUT) -0.5 V to VCC + 0.5 V Ambient Temperature (TA) Storage Temperature ECL Signal Output Current ESD Protection o o -65 C to 150 C -50mA 2000 V Min 4.75 Typ 5.0 Max Units 5.
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9.0 Electrical Specifications (Continued) 9.1 DC Electrical Specification Symbol VIH VIL VIM IIH Pin Types Parameter I I/O I/O, Z Input High Voltage Min Typ Max Units 2.0 V AN0 and AN1 VCC - 1.0 V X1 VCC - 1.0 V I I/O I/O, Z Input Low Voltage 0.8 V AN0 and AN1 1.0 V X1 1.0 V (VCC/2) +0.5 V 10 µA -100 µA 10 µA X2 = N.C. 100 µA 0.4 V AN0 and AN1 Input Mid Level Voltage I I/O I/O, Z I I/O I/O, Z Pin Unconnected (VCC/2) -0.
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9.
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9.0 Electrical Specifications (Continued) 9.2 CGM Clock Timing X1 IN TX_CLK OUT T2.0.2 T2.0.1 Parameter Description Notes Min Typ Max Units T2.0.1 X1 to TX_CLK Delay -3 +3 ns T2.0.2 TX_CLK Duty Cycle 35 65 % Max Units 300 ns 9.3 MII Serial Management AC Timing MDC T3.0.1 T3.0.4 MDIO (OUTPUT) MDC T3.0.2 MDIO (INPUT) Parameter Description T3.0.3 VALID DATA Notes Min Typ T3.0.1 MDC to MDIO (Output) Delay Time 0 T3.0.2 MDIO (Input) to MDC Setup Time 10 ns T3.0.
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9.0 Electrical Specifications (Continued) 9.4 100 Mb/s AC Timing 9.4.1 100 Mb/s MII Transmit Timing TX_CLK T4.1.1 TXD[3:0] TX_EN TX_ER Parameter T4.1.2 VALID DATA Description T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK T4.1.2 TXD[4:0] Data Hold from TX_CLK Notes Min Typ Max Units 100 Mb/s Normal mode 14 ns TXD[4:0] Data Setup to TX_CLK 100 Mb/s Symbol mode 10 ns TXD[3:0], TX_EN, TX_ER Data Hold from TX_CLK 100 Mb/s Normal mode -1 ns 100 Mb/s Symbol mode -1 ns 9.4.
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9.0 Electrical Specifications (Continued) 9.4.3 100BASE-TX Transmit Packet Latency Timing TX_CLK TX_EN TXD TPTD+/- Parameter T4.3.1 T4.3.1 IDLE (J/K) Description TX_CLK to TPTD+/− Latency Notes DATA Min Typ Max Units 100 Mb/s Normal mode 6.0 bits 100 Mb/s Symbol mode 6.0 bits Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “j” code group as output from the TPTD± pins.
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9.0 Electrical Specifications (Continued) 9.4.4 100BASE-TX Transmit Packet Deassertion Timing TX_CLK TXD TX_EN T4.4.1 TPTD+/- Parameter T4.4.1 DATA (T/R) Description Notes TX_CLK to TPTD+/− Deassertion IDLE Min Typ Max Units 100 Mb/s Normal mode 6.0 bits 100 Mb/s Symbol mode 6.0 bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the TPTD± pins.
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9.0 Electrical Specifications (Continued) 9.4.5 100BASE-TX Transmit Timing TPTD+/+1 RISE -1 RISE -1 FALL +1 FALL T4.5.2 T4.5.1 T4.5.1 T4.5.1 T4.5.1 TPTD+/EYE PATTERN T4.5.2 Parameter T4.5.1 T4.5.2 Description Min Typ Max Units 3 4 5 ns 100 Mb/s Rise/Fall Mismatch 500 ps 100 Mb/s TPTD+/− Transmit Jitter 1.4 ns 100 Mb/s TPTD+/− Rise and Fall Times Notes see Test Conditions section Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
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9.0 Electrical Specifications (Continued) 9.4.6 100BASE-TX Receive Packet Latency Timing TPRD+/- IDLE DATA (J/K) T4.6.1 CRS T4.6.2 RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description Notes Min Typ Max Units T4.6.1 Carrier Sense on Delay 100 Mb/s Normal mode 17.5 bits T4.6.
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9.0 Electrical Specifications (Continued) 9.4.8 100BASE-FX Transmit Packet Latency Timing TX_CLK TX_EN TXD T4.8.1 FXTD+/- Parameter T4.8.1 IDLE (J/K) Description TX_CLK to FXTD+/− Latency Notes DATA Min Typ Max Units 100 Mb/s Normal mode 4.0 bits 100 Mb/s Symbol mode 4.0 bits Note: For Normal mode, Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “j” code group as output from the FXTD± pins.
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9.0 Electrical Specifications (Continued) 9.4.9 100BASE-FX Transmit Packet Deassertion Timing TX_CLK TXD TX_EN T4.9.1 FXTD+/- Parameter T4.9.1 DATA (T/R) Description Notes TX_CLK to FXTD+/− Deassertion IDLE Max Units 100 Mb/s Normal mode Min Typ 4.0 bits 100 Mb/s Symbol mode 4.0 bits Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the FXTD± pins.
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9.0 Electrical Specifications (Continued) 9.4.11 100BASE-FX Receive Packet Deassertion Timing FXRD+/- DATA IDLE (T/R) T4.11.1 CRS RXD[3:0] RX_DV RX_ER/RXD[4] Parameter T4.11.1 Description Carrier Sense Off Delay Notes Min Typ 100 Mb/s Normal mode Max Units 21.5 bits Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense. Note: 1 bit time = 10 ns in 100 Mb/s mode. 9.5 10 Mb/s AC Timing 9.5.
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9.0 Electrical Specifications (Continued) 9.5.13 10 Mb/s MII Receive Timing RX_EN T5.13.4 T5.13.1 T5.13. 2 RX_CLK T5.13.3 RXD[3:0] RX_DV RX_ER VALID DATA Parameter Description Notes Min Typ Max Units T5.13.1 RX_EN to RX_CLK, RXD[3:0], RX_DV Active All 10 Mb/s modes 10 ns T5.13.2 RX_EN to RX_CLK, RXD[3:0], RX_DV TRISTATE 25 ns T5.13.3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 10 Mb/s Nibble mode 210 ns RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 10 Mb/s Serial mode 40 60 ns T5.13.
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9.0 Electrical Specifications (Continued) 9.5.15 10BASE-T Transmit Timing (End of Packet) T5.15.1 TX_CLK TX_EN 0 T5.15.2 0 TPTD+/- TPTD+/- Parameter T5.15.1 T5.15.2 T5.15.3 1 T5.15.
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9.0 Electrical Specifications (Continued) 9.5.16 10BASE-T Receive Timing (Start of Packet) 1ST SFD BIT DECODED 1 0 1 TPRD+/T5.16.1 CRS T5.16. RX_CLK T5.16.4 RXD T5.16. RX_DV Parameter Description Notes Min Typ Max Units 1 µs T5.16.1 Carrier Sense Turn On Delay (TPRD+/− to CRS) 10 Mb/s Nibble mode 10 Mb/s Serial mode 1 µs T5.16.2 Decoder Acquisition Time 10 Mb/s Nibble mode 3.6 µs 10 Mb/s Serial mode 3.2 µs 10 Mb/s Nibble mode 17.
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9.0 Electrical Specifications (Continued) 9.5.18 10 Mb/s AUI Timing 1 0 T5.18. 0 AUITD+/T5.18. T5.18. AUIRD+/- Parameter Description T5.18.1 AUI Transmit Output High Before Idle T5.18.2 AUI Transmit Output Idle Time T5.18.3 AUI Receive End of Packet Hold Time Notes Min Typ Max 200 Units ns 8000 225 ns ns Note: The worst case for T5.18.1 is data ending in a ‘0’. 9.5.19 10 Mb/sHeartbeat Timing TXE TXC T5.19. T5.19. COL Parameter T5.19.1 T5.19.
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9.0 Electrical Specifications (Continued) 9.5.20 10 Mb/s Jabber Timing TXE T5.20.1 T5.20. TPTD+/- COL Parameter T5.20.1 T5.20.2 Description Notes Jabber Activation Time Jabber Deactivation Time Min Typ Max Units 10 Mb/s Nibble mode 26 ms 10 Mb/s Serial mode 26 ms 10 Mb/s Nibble mode 500 ms 10 Mb/s Serial mode 500 ms 9.5.21 10BASE-T Normal Link Pulse Timing T5.21.2 T5.21.1 Parameter Description T5.21.1 Pulse Width T5.21.
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9.0 Electrical Specifications (Continued) 9.6 Auto-Negotiation Fast Link Pulse (FLP) Timing T6.21. T6.21. T6.21. 1 T6.21.1 FAST LINK PULSE(S) CLOCK PULSE DATA PULSE CLOCK PULSE T6.21. T6.21.4 T6.21.5 FLP BURST Parameter FLP BURST Description T6.21.1 Clock, Data Pulse Width T6.21.2 Clock Pulse to Clock Pulse Period T6.21.3 Clock Pulse to Data Pulse Period T6.21.4 Number of Pulses in a Burst T6.21.5 Burst Width T6.21.
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9.0 Electrical Specifications (Continued) 9.7.22 100BASE-X CRM Acquisition Time FXSD+ OR SD+ INTERNAL T7.22.1 FXRD+/- Parameter T7.22.1 PLL PRIOR TO LOCK Description CRM Acquisition PLL LOCKED Notes Min Typ 100 Mb/s Max Units 250 µs Note: The Clock Generation Module (CGM) must be stable for at least 100 µs before the Clock Recovery Module (CRM) can lock to receive data. Note: SD+ internal comes from the internal Signal Detect function block when in 100BASE-TX mode. 9.7.
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9.0 Electrical Specifications (Continued) 9.8 Reset Timing VCC T8.23. T8.23. T8.23. HARDWARE RESET (OPTION #1) HARDWARE RESET (OPTION #2) 32 CLOCKS MDC T8.23. LATCH-IN OF HARDWARE CONFIGURATION PINS T8.23.5 INPUT OUTPUT DUAL FUNCTION PINS BECOME ENABLED AS OUTPUTS Parameter Description Notes Min Typ Max Units 500 µs 1 µs 500 µs T8.23.1 Internal Reset Time T8.23.2 Hardware RESET Pulse Width T8.23.
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9.0 Electrical Specifications (Continued) 9.9 Loopback Timing TX_CLK TX_EN TXD[3:0] CRS T9.23.1 RX_CLK RX_DV RXD[3:0] Parameter T9.23.1 Description TX_EN to RX_DV Loopback Notes Min Typ Max Units 100 Mb/s 240 ns 10 Mb/s Serial mode 650 ns 10 Mb/s Nibble mode 2 µs Note: Due to the nature of the descrambler function, all 100BASE-X Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs.
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9.0 Electrical Specifications (Continued) 9.10 Isolation Timing CLEAR BIT 10 OF BMCR (RETURN TO NORMAL OPERATION FROM ISOLATE MODE) T10.23.1 H/W OR S/W RESET (WITH PHYAD ≠ 00000) T10.23.2 MODE ISOLATE Parameter Description Notes Max Units T10.23.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode 100 µs T10.23.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs 84 Min NORMAL Typ www.national.
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10.0 Test Conditions This section contains information relating to the specific test environments, including stimulus and loading parameters, for the DP83843. These test conditions are categorized in the following subsections by each type of pin/interface including: of this load is 50 pF. The diagram in Figure 28 illustrates the test configuration. It should be noted that the current source and sink limits are set to 4.0 mA when testing/loading the MII output pins.
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10.0 Test Conditions (Continued) AUITD/FXTD+ DP83843 PHYTER AUITD/FXTD- 50Ω 50Ω VTT = VCC - 2.2V VTT VTT Figure 27. 100BASE-FX Test Load VCC CURRENT SOUR 50pF DP83843 PHYTER CMOS OUTPUT 50pF CURRENT SINK GND Figure 28. CMOS Output Test Load TPTD+ 100Ω DP83843 PHYTER 100Ω TPTD10/100 AC COUPLING TRANSFORMER Figure 29. 10/100 Twisted Pair Load (zero meters) 86 www.national.
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DP83843 PHYTER 11.0 Package Dimensions inches (millimeters) unless otherwise noted Molded Plastic Quad Flat Package Order Number DP83843BVJE NC Package Number VJE80A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.