Datasheet

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4.0 Register Set (Continued)
DP83816
4.1.8 Boot ROM Configuration Register
4.1.9 Capabilities Pointer Register
This register stores the capabilities linked list offset into the PCI configuration space.
Tag: CFGROM Size: 32 bits Hard Reset: 00000000h
Offset: 30h Access: Read Write Soft Reset: unchanged
Bit Bit Name Description
31-16 ROMBASE ROM Base Address
Set to the base address for the boot ROM.
15-11 ROMSIZE ROM Size
Set to 0 indicating a requirement for 64K bytes of Boot ROM space. Read only.
10-1 unused
(reads return 0)
0 ROMEN ROM Enable
This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83816 to share the
address decode logic between the boot ROM and itself. The BIOS will copy the contents of the boot
ROM to system RAM before executing it. Set to 1 enables the address decode for boot ROM disabling
access to operational target registers.
Tag: CAPPTR Size: 32 bits Hard Reset: 00000040h
Offset: 34h Access: Read Only Soft Reset: unchanged
Bit Bit Name Description
31-8 unused
(reads return 0)
7-0 CLOFS Capabilities List Offset
Offset into PCI configuration space for the location of the first item in the Capabilities Linked List, set to
40h to point to the PMCAP register.