Datasheet

DP83640

SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013

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Table 10-21. PHY Control Register (PHYCR), address 0x19 (continued)

Bit Bit Name Default Description

13 PAUSE_RX 0, RO Pause Receive Negotiated:

Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10]

and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,

“Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a

full duplex technology.

12 PAUSE_TX 0, RO Pause Transmit Negotiated:

Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10]

and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,

Pause Resolution, only if the Auto-Negotiated Highest Common Denominator is a

full duplex technology.

11 BIST_FE 0, RW/SC BIST Force Error:

1 = Force BIST Error.

0 = Normal operation.

This bit forces a single error, and is self clearing.

10 PSR_15 0, RW BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected.

9 BIST_STATUS 0, LL/RO BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared when a BIST failure occurs or BIST is stopped.

For a count number of BIST errors, see the BIST Error Count in the CDCTRL1

8 BIST_START 0, RW BIST Start:

Writes:

1 = BIST start. Writing 1 to this bit enables transmission of BIST packets and

enables the receive BIST engine to start looking for packet traffic.

0 = BIST stop. Stop the BIST. Writing 0 to this bit also clears the BIST_STATUS bit.

Reads:

1 = BIST active. This bit reads 1 after the transmit BIST engine has been enabled

and the receive BIST engine has detected packet traffic.

0 = BIST inactive. This bit will read 0 if the BIST is disabled or if the BIST is enabled

but no receive traffic has been detected.

7 BP_STRETCH 0, RW Bypass LED Stretching:

This will bypass the LED stretching and the LEDs will reflect the internal value.

1 = Bypass LED stretching.

0 = Normal operation.

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