Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Table 10-19. RMII and Bypass Register (RBR), address 0x17 (continued)
Bit Bit Name Default Description
13 DIS_TX_OPT 0, RW Disable RMII TX Latency Optimization:
Normally the RMII Transmitter will minimize the transmit latency by realigning the
transmit clock with the reference clock phase at the start of a packet transmission.
Setting this bit will disable phase realignment and ensure that IDLE bits will always
be sent in multiples of the symbol size. This will result in a larger uncertainty in
RMII transmit latency.
12:9 RESERVED 0000, RW RESERVED: Must be 0.
8 PMD_LOOP 0, RW PMD Loopback:
0 = Normal Operation.
1 = Remote (PMD) Loopback.
Setting this bit will cause the device to Loopback data received from the Physical
Layer. The loopback is done prior to the MII or RMII interface. Data received at the
internal MII or RMII interface will be applied to the transmitter. This mode should
only be used if RMII mode or Single Clock MII mode is enabled.
7 SCMII_RX 0, RW Single Clock RX MII Mode:
0 = Standard MII mode.
1 = Single Clock RX MII Mode.
Setting this bit will cause the device to generate receive data (RX_DV, RX_ER,
RXD[3:0]) synchronous to the X1 Reference clock. RX_CLK is not used in this
mode. This mode uses the RMII elasticity buffer to tolerate variations in clock
frequencies. This bit cannot be set if RMII_MODE is set to a 1.
6 SCMII_TX 0, RW Single Clock TX MII Mode:
0 = Standard MII mode.
1 = Single Clock TX MII Mode.
Setting this bit will cause the device to sample transmit data (TX_EN, TXD[3:0])
synchronous to the X1 Reference clock. TX_CLK is not used in this mode. This bit
cannot be set if RMII_MODE is set to a 1.
5 RMII_MODE Strap, RW Reduced MII Mode:
0 = Standard MII Mode.
1 = Reduced MII Mode.
4 RMII_REV1_0 0, RW Reduced MII Revision 1.0:
This bit modifies how CRS_DV is generated.
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate
deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
3 RX_OVF_STS 0, RO RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
2 RX_UNF_STS 0, RO RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency variation
tolerance between the 50 MHz RMII clock and the recovered data. See Section 6.2
for more information on Elasticity Buffer settings in RMII mode. See Section 6.3 for
more information on Elasticity Buffer settings in SCMII mode.
96 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
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