Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (continued)
Bit Bit Name Default Description
7 DESC_TIME 0, RW Descrambler Timeout:
Increase the descrambler timeout. When set, this allows the device to receive larger
packets (>9k bytes) without loss of synchronization.
1 = 2 ms.
0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
6 FX_EN Strap, RW FX Fiber Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
Write PHYCR2[9], SOFT_RESET, after enabling or disabling Fiber Mode via register
access to ensure correct configuration.
1 = Enables FX operation.
0 = Disables FX operation.
5 FORCE_100_OK 0, RW Force 100 Mb/s Good Link:
OR’ed with MAC_FORCE_LINK_100 signal.
1 = Forces 100 Mb/s Good Link.
0 = Normal 100 Mb/s operation.
4 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
3 FEFI_EN Strap, RW Far End Fault Indication Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
1 = FEFI Mode Enabled.
0 = FEFI Mode Disabled.
2 NRZI_BYPASS 0, RW NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1 SCRAM Strap, RW Scrambler Bypass Enable:
BYPASS
This bit is set when the FX_EN strap option is selected. In the FX mode, the
scrambler is bypassed.
1 = Scrambler Bypass Enabled.
0 = Scrambler Bypass Disabled.
0 DESCRAM Strap, RW Descrambler Bypass Enable:
BYPASS
This bit is set when the FX_EN strap option is selected. In the FX mode, the
descrambler is bypassed.
1 = Descrambler Bypass Enabled.
0 = Descrambler Bypass Disabled.
10.2.4 RMII and Bypass Register (RBR)
This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII,
RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to
allow datapath selection for Transmit and Receive in multiport applications.
Table 10-19. RMII and Bypass Register (RBR), address 0x17
Bit Bit Name Default Description
15 RESERVED 0, RW RESERVED: Must be 0.
14 RMII_MASTER Strap, RW RMII Master Mode:
Setting this bit allows the core to use a 25 MHz input reference clock and generate
its own 50 MHz RMII reference clock. The generated RMII reference clock will also
be used by the attached MAC.
1 = RMII Master Mode (25 MHz input reference)
0 = RMII Slave Mode (50 MHz input reference)
Note: Due to clock muxing and divider operation, this bit should normally only be
reconfigured via the strap option.
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