Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
10.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
This register contains the next page information sent by this device to its Link Partner during Auto-
Negotiation.
Table 10-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
13 MP 1, RW Message Page:
1 = Message Page.
0 = Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that Local Device has
the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word was 0.
0 = Value of toggle bit in previously transmitted Link Code Word was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to ensure
synchronization with the Link Partner during Next Page exchange. This bit shall
always take the opposite value of the Toggle bit in the previously exchanged Link
Code Word.
10:0 CODE 000 0000 0001, RW Code:
This field represents the code field of the next page transmission. If the MP bit is
set (bit 13 of this register), then the code shall be interpreted as a "Message
Page”, as defined in Annex 28C of IEEE 802.3u. Otherwise, the code shall be
interpreted as an "Unformatted Page”, and the interpretation is application
specific.
The default value of the CODE represents a Null Page as defined in Annex 28C
of IEEE 802.3u.
10.1.10 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed
information.
Table 10-12. PHY Status Register (PHYSTS), address 0x10
Bit Bit Name Default Description
15 RESERVED 0, RO RESERVED: Write ignored, read as 0.
14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits
in the PHYCR register. When MDIX is enabled, but not forced, this bit will
update dynamically as the Auto-MDIX algorithm swaps between MDI and MDIX
configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TPRD pair, Transmit on TPTD pair)
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 89
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