Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Table 10-4. Basic Mode Status Register (BMSR), address 0x01 (continued)
Bit Bit Name Default Description
4 REMOTE FAULT 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End
Fault Indication or notification from Link Partner of Remote Fault.
0 = No remote fault condition detected.
3 AUTO-NEGOTIATION 1, RO/P Auto Negotiation Ability:
ABILITY
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2 LINK STATUS 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link validity is implementation specific. The occurrence of a link failure
condition will causes the Link Status bit to clear. Once cleared, this bit may only be set by
establishing a good link condition and a read via the management interface.
1 JABBER DETECT 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence of a jabber
condition causes it to set until it is cleared by a read to this register by the management
interface or by a reset.
0 EXTENDED 1, RO/P Extended Capability:
CAPABILITY
1 = Extended register capabilities.
0 = Basic register set capabilities only.
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83640. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number
and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY
Identifier if desired. The PHY Identifier is intended to support network management. Texas Instruments's
IEEE assigned OUI is 080017h.
10.1.3 PHY Identifier Register #1 (PHYIDR1)
Table 10-5. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit Bit Name Default Description
15:0 OUI_MSB 0010 0000 0000 0000, OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15
RO/P to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE
standard refers to these as bits 1 and 2).
10.1.4 PHY Identifier Register #2 (PHYIDR2)
Table 10-6. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit Bit Name Default Description
15:10 OUI_LSB 0101 11, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register
respectively.
9:4 VNDR_MDL 00 1110, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to
bit 9).
3:0 MDL_REV 0001, RO/P Model Revision Number:
Four bits of the vendor model revision number are mapped from bits 3 to 0 (most
significant bit to bit 3). This field will be incremented for all major device changes.
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 85
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