Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
6.5 PHY Control Frames
The DP83640 supports a packet-based control mechanism for use in situations where the Serial
Management Interface is not available or does not provide enough throughput. Application software may
build a packet, called a PHY Control Frame (PCF), to be passed to the PHY through the MAC Transmit
Data interface. The PHY will intercept these packets and use them to assert writes to Management
Registers as if they occurred via the Management Interface. Multiple register writes may be incorporated
in a single frame.
The PHY Control Frame may also be used to read a register location. The read value will be returned in a
PHY Status Frame if that function is enabled. Only a single read may be outstanding at any time, so only
one read should be included in a single PHY Control Frame.
The PHY Control Frame block performs the following functions:
• Parse incoming transmit packets to detect PHY Control Frames
• Truncate PHY Control Frames to prevent complete frame from reaching the transmit physical medium
• Buffer up to 15 bytes of the Frame to be intercepted by the PHY with no portion reaching physical
medium
• Detect commands in the PHY Control Frame and pass them to the register block
• Check CRC to detect error conditions
• Report CRC and invalid command errors to the system via register status and/or interrupt
PHY Control Frames can be enabled through the PCF_Enable bit in the PHY Control Frames
Configuration Register (PCFCR). PHY Control Frames can also be enabled by using the PCF_EN strap
option. For a more detailed discussion on the use of PHY Control Frames, refer to the Software
Development Guide for the DP83640.
6.6 PHY Status Frames
The DP83640 implements a packet-based status mechanism that allows the PHY to queue up events and
pass them to the microcontroller through the receive data interface. The packet, called a PHY Status
Frame, may be used to provide IEEE 1588 status for transmit packet timestamps, receive packet
timestamps, event timestamps, and trigger conditions. In addition the device can generate status
messages indicating packet buffering errors and to return data read using the PHY Control Frame register
access mechanism.
Each PHY Status Frame may include multiple status messages. The packet will be framed such that it will
look like a IEEE 1588 frame to ensure that it will get to the IEEE 1588 software stack. The PHY will
provide buffering of any incoming packet to allow the status packet to be passed to the MAC.
Programmable inter-frame gap and preamble length allow the PHY to recover lost bandwidth in the case
of heavy receive traffic.
In a PHY Status Frame, status messages are not provided in a chronological order. Instead, they are
provided in the following order of priority:
1. PHY Control Frame Read Data
2. Packet Buffer Error
3. Transmit Timestamp
4. Receive Timestamp
5. Trigger Status
6. Event Timestamp
Each of the message types may be individually enabled, allowing options on which functions may be
delivered in a PHY Status Frame.
Timestamps that are delivered via PHY Status Frames will not be reflected in the corresponding status
and timestamp registers nor will they generate an interrupt.
Copyright © 2007–2013, Texas Instruments Incorporated MAC Interface 57
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