Datasheet

DP83640

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SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013

• Transmit Channel Select: The transmitter can send pulses down either the transmit pair or the

receive pair by enabling bit 13 of TDR_CTRL (16h). Default value is to select the transmit pair.

The following receive mode controls are available:

• Min/Max Mode Control: Bit 7 of TDR_CTRL (16h) controls the TDR Monitor operation. In default

mode, the monitor will detect maximum (positive) values. In Min Mode, the monitor will detect minimum

(negative) values.

• Receive Channel Select: The receiver can monitor either the transmit pair or the receive pair by

enabling bit 12 of TDR_CTRL (16h). Default value is to select the transmit pair.

• Receive Window: The receiver can monitor receive data within a programmable window using the

TDR Window Register (TDR_WIN), address 17h. The window is controlled by two register values: TDR

Start Window, bits [15:8] of TDR_WIN (17h) and TDR Stop Window, bits [7:0] of TDR_WIN (17h). The

TDR Start Window indicates the first clock to start sampling. The TDR Stop Window indicates the last

clock to sample. By default, the full window is enabled, with Start set to 0 and Stop set to 255. The

window range is in 8 ns clock increments, so the maximum window size is 2048 ns.

5.10.7 TDR Results

The results of a TDR peak and threshold measurement are available in the TDR Peak Measurement

19h. The threshold measurement may be a more accurate method of measuring the length of longer

cables since it provides a better indication of the start of the received pulse, rather than the peak value.

Software utilizing the TDR function should implement an algorithm to send TDR pulses and evaluate

results. Multiple runs should be used to best qualify any received pulses as multiple reflections could exist.

In addition, when monitoring the transmitting pair, the window feature should be used to disqualify the

transmitted pulse. Multiple runs may also be used to average the values providing more accurate results.

Actual distance measurements are dependent on the velocity of propagation of the cable. The delay value

is typically on the order of 4.6 to 4.9 ns/m.

5.11 BIST

The DP83640 incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths.

BIST testing can be performed with the part in the internal loopback mode or externally looped back using

a loopback cable fixture. BIST testing can also be performed between two directly connected DP83640

devices.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating

a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random

sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to

the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the

BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit

defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,

the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data

transmission by setting the BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).

The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits

[15:8].

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