Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
5.6 Half Duplex vs. full Duplex
The DP83640 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex
mode, Carrier Sense (CRS) responds to both transmit and receive activity in order to maintain compliance
with the IEEE 802.3 specification.
Since the DP83640 is designed to support simultaneous transmit and receive activity it is capable of
supporting full-duplex switched applications with a throughput of up to 200 Mb/s when operating in either
100BASE-TX or 100BASE-FX. Because the CSMA/CD protocol does not apply to full-duplex operation,
the DP83640 disables its own internal collision sensing and reporting functions and modifies the behavior
of CRS such that it indicates only receive activity. This allows a full-duplex capable MAC to operate
properly.
All modes of operation (100BASE-TX, 100BASE-FX, 10BASE-T) can run either half-duplex or full-duplex.
Additionally, other than CRS and collision reporting, all remaining MII signaling remains the same
regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can
interpret and configure to full-duplex operation, parallel detection can not recognize the difference between
full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the
802.3u specification, if a far-end link partner is configured to a forced full-duplex 100BASE-TX ability, the
parallel detection state machine in the partner would be unable to detect the full-duplex capability of the
far-end link partner. This link segment would negotiate to a half-duplex 100BASE-TX configuration (same
scenario for 10 Mb/s).
Auto-Negotiation is not supported in 100BASE-FX operation. Selection of Half or Full-duplex operation is
controlled by bit 8 of the Basic Mode Control Register (BMCR), address 00h. If 100BASE-FX mode is
strapped using the RX_ER pin, the AN0 strap value is used to set the value of bit 8 of the BMCR (00h)
register. Note that the other Auto-Negotiation strap pins (AN_EN and AN1) are ignored in 100BASE-FX
mode.
5.7 Internal Loopback
The DP83640 includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is
selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit
enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3
of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the
media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled
before selecting the Loopback mode.
5.8 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin
functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR
(11h) will configure the pin as an active low interrupt output.
5.8.1 Power Down Control Mode
The PWRDOWN/INTN pin can be asserted low to put the device in a Power Down mode. This is
equivalent to setting bit 11 (POWER DOWN) in the Basic Mode Control Register, BMCR (00h). An
external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor.
Alternatively, the device can be configured to initialize into a Power Down state by use of an external pull-
down resistor on the PWRDOWN/INTN pin. Since the device will still respond to management register
accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN/INTN input, allowing
the device to exit the Power Down state.
46 Configuration Copyright © 2007–2013, Texas Instruments Incorporated
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