Datasheet

DP83640

SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013

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When in the MII Isolate Mode, the DP83640 does not respond to packet data present at TXD[3:0] and

TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],

COL, and CRS/CRS_DV outputs. When in Isolate Mode, the DP83640 will continue to respond to all serial

management transactions over the MII.

While in Isolate Mode, the PMD output pair will not transmit packet data but will continue to source

100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83640 can Auto-Negotiate or parallel detect to a specific technology depending on the receive

signal at the PMD input pair. A valid link can be established for the receiver even when the DP83640 is in

Isolate Mode.

5.4.2 Broadcast Mode

The DP83640 is also capable of accepting broadcast messages (register writes to PHY address 0x1F).

Setting the BC_WRITE to 1, bit 11 of the PHY Control Register 2 (PHYCR2) at address 0x1C, will

configure the device to accept broadcast messages independent of the local PHY Address value.

5.5 LED Interface

The DP83640 supports three configurable Light Emitting Diode (LED) pins: LED_LINK,

LED_SPEED/FX_SD, and LED_ACT.

Several functions can be multiplexed onto the three LEDs using three different modes of operation. The

LED operation mode can be selected by writing to the LED_CFG[1:0] register bits in the PHY Control

cannot be set by a strap pin.

See Table 5-3 for LED Mode selection.

Table 5-3. LED Mode Selection

Mode LED_CFG[1] LED_CFG[0] LED_LINK LED_SPEED LED_ACT

1 don't care 1 ON for Good Link ON in 100 Mb/s ON for Activity

OFF for No Link OFF in 10 Mb/s OFF for No Activity

2 0 0 ON for Good Link ON in 100 Mb/s ON for Collision

BLINK for Activity OFF in 10 Mb/s OFF for No Collision

3 1 0 ON for Good Link ON in 100 Mb/s ON for Full Duplex

BLINK for Activity OFF in 10 Mb/s OFF for Half Duplex

The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-TX mode, link is

established as a result of input receive amplitude compliant with the TP-PMD specifications which will

result in internal generation of signal detect. A 10 Mb/s Link is established as a result of the reception of at

least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause

the assertion of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified

in the IEEE 802.3 specification. In 100BASE-TX mode, an optional fast link loss detection may be enabled

by setting the SD_TIME control in the SD_CNFG register. Enabling fast link loss detection will result in the

LED_LINK deassertion within approximately 1.3 µs of loss of signal on the wire.

The LED_LINK pin in Mode 1 will be OFF when no LINK is present.

The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate

activity is present on activity. The BLINK frequency is defined in BLINK_FREQ, bits [7:6] of register

LEDCR (18h).

Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0,

Activity is signaled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive.

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