Datasheet

DataIDLE Data(J/K) (TR)
T2.26.4
T2.26.1
T2.26.5
T2.26.3
T2.26.2
T2.26.2
PMD Input
Pair
X1
CRS/CRS_DV
RXD[1:0]
RX_ER
DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
4.30 AC Specifications — RMII Receive Timing (Slave Mode)
Parameter Description
(1)
Notes Min Typ Max Units
T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.26.2 RXD[1:0], CRS_DV, and RX_ER 2 14 ns
output delay from X1 rising edge
(2)
T2.26.3 CRS ON delay
(3)
100BASE-TX mode 18.5 bits
100BASE-FX mode 9
T2.26.4 CRS OFF delay
(4)
100BASE-TX mode 27 bits
100BASE-FX mode 17
T2.26.5 RXD[1:0] and RX_ER 100BASE-TX mode 38 bits
latency
(5)(6)(7)
100BASE-FX mode 27
(1) Per the RMII Specification, output delays assume a 25 pF load.
(2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS de-assertion.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
(6) Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.
(7) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive
datapath.
Figure 4-26. RMII Receive Timing (Slave Mode)
36 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
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