Datasheet

TX_CLK
TX_EN
TXD[3:0]
PMD Output
Pair
IDLE DATA(J/K)
T2.6.1
Valid Data
T2.5.1T2.5.1
T2.5.2
RX_CLK
RXD[3:0]
RX_DV
RX_ER
DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
4.9 AC Specifications — 100 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.5.1 RX_CLK High/Low Time
(1)
100 Mb/s Normal mode 16 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER 100 Mb/s Normal mode 10 30 ns
Delay
(1) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
Figure 4-5. 100 Mb/s MII Receive Timing
4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency
Timing
Parameter Description
(1)
Notes
(2)
Min Typ Max Units
T2.6.1 TX_CLK to PMD Output Pair Latency 100BASE-TX and 100BASE-FX modes 5 bits
IEEE 1588 One-Step Operation enabled 9 bits
(1) Enabling PHY Control Frames will add latency equal to 8 bits times the PCF_BUF_SIZE setting. For example if PCF_BUF_SIZE is set
to 15, then the additional delay will be 15*8= 120 bits.
(2) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Figure 4-6. 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing
24 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
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