Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Signal Name Pin Name Type Pin # Description
FX_EN_Z RX_ER S, O, PU 41 FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode.
This mode is disabled by default. An external pull-down will enable
100Base-FX mode.
LED_CFG CRS/CRS_DV S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can
be controlled via the strap option. All modes are configurable via
register access.
See Table 5-3 for LED Mode Selection.
MII_MODE RX_DV S, O, PD 39 MII MODE SELECT: This strapping option determines the operating
mode of the MAC Data Interface. Default operation is MII Mode with a
value of 0 due to the internal pulldown. Strapping MII_MODE high will
cause the device to be in RMII mode of operation.
MII_MODE MAC Interface Mode
0 MII Mode
1 RMII Mode
PCF_EN GPIO2 S, I, PD 22 PHY CONTROL FRAME ENABLE: When high, allows the DP83640 to
respond to PHY Control Frames.
RMII_MAS TXD_3 S, I, PD 6 RMII MASTER ENABLE: When MII_MODE is strapped high, this
strapping option enables RMII Master mode, in which the DP83640
uses a 25 MHz crystal connection on X1/X2 and generates the 50 MHz
RMII reference clock. If strapped low when MII_MODE is strapped high,
default RMII operation (RMII Slave) is enabled, in which the DP83640
uses a 50 MHz oscillator input on X1 as the RMII reference clock. This
strap option is ignored if the MII_MODE strap is low.
3.11 10 Mb/s and 100 Mb/s PMD Interface
Signal Name Pin Name Type Pin # Description
TD- TD- I/O 16 Differential common driver transmit output (PMD Output Pair). These
TD+ TD+ 17 differential outputs are automatically configured to either 10BASE-T or
100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input
pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
These pins require 3.3V bias for operation.
RD- RD- I/O 13 Differential receive input (PMD Input Pair). These differential inputs are
RD+ RD+ 14 automatically configured to accept either 100BASE-TX or 10BASE-T
signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit
Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
FX_SD LED_SPEED/FX_S S, I/O, PU 27 FIBER MODE SIGNAL DETECT: This pin provides the Signal Detect input
D for 100BASE-FX mode.
3.12 Power Supply Pins
Signal Name Pin Name Type Pin # Description
ANAVSS ANAVSS Ground 18 Analog Ground
ANA33VDD ANA33VDD Supply 19 Analog VDD Supply
CD_VSS CD_VSS Ground 15 Analog Ground
IO_CORE_VSS IO_CORE_VSS Ground 35 Digital Ground
IO_VDD IO_VDD Supply 32 I/O VDD Supply
48
IO_VSS IO_VSS Ground 47 Digital Ground
VREF VREF 20 Bias Resistor Connection. A 4.87 kΩ 1% resistor should be connected from
VREF to GND.
18 Pin Descriptions Copyright © 2007–2013, Texas Instruments Incorporated
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