Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Signal Name Pin Name Type Pin # Description
LED_ACT LED_ACT S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when
activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates
Collision detection. In Mode 3, this LED output indicates Full-Duplex status.
3.7 IEEE 1588 Event/Trigger/Clock Interface
Signal Name Pin Name Type Pin # Description
GPIO1 GPIO1 I/O, PD 21 General Purpose I/O: These pins may be used to signal or detect events.
GPIO2 GPIO2 22
GPIO3 GPIO3 23
GPIO4 GPIO4 25
GPIO5 LED_ACT I/O, PU 26 General Purpose I/O: These pins may be used to signal or detect events.
GPIO6 LED_SPEED/FX_S 27 Care should be taken when designing systems that use LEDs but use these
D pins as GPIOs. To disable the LED functions, refer to Section 10.2.5.
GPIO7 LED_LINK 28
GPIO8 GPIO8 I/O, PD 36 General Purpose I/O: These pins may be used to signal or detect events.
GPIO9 GPIO9 37
GPIO10 TDO I/O, PU 9 General Purpose I/O: These pins may be used to signal or detect events.
GPIO11 TDI 12 Care should be taken when designing systems that use the JTAG interface
but use these pins as GPIOs.
GPIO12 CLK_OUT I/O, PD 24 General Purpose I/O: This pin may be used to signal or detect events or
may output a programmable clock signal synchronized to the internal IEEE
1588 clock or may be used as an input for an externally generated IEEE
1588 reference clock. If the system does not require the CLK_OUT signal,
the CLK_OUT output should be disabled via the CLK_OUT_EN strap.
3.8 JTAG Interface
Signal Name Pin Name Type Pin # Description
TCK TCK I, PU 8 TEST CLOCK
This pin has a weak internal pullup.
TDO TDO O 9 TEST OUTPUT
TMS TMS I, PU 10 TEST MODE SELECT
This pin has a weak internal pullup.
TRST# TRST# I, PU 11 TEST RESET: Active low test reset.
This pin has a weak internal pullup.
TDI TDI I, PU 12 TEST DATA INPUT
This pin has a weak internal pullup.
3.9 Reset and Power Down
Signal Name Pin Name Type Pin # Description
RESET_N RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83640.
Asserting this pin low for at least 1 µs will force a reset process to occur.
All internal registers will re-initialize to their default states as specified for
each bit in the Register Block section. All strap options are re-initialized as
well.
PWRDOWN/INTN PWRDOWN/INTN I, PU 7 The default function of this pin is POWER DOWN.
POWER DOWN: Asserting this signal low enables the DP83640 Power
Down mode of operation. In this mode, the DP83640 will power down and
consume minimum power. Register access will be available through the
Management Interface to configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead
of a Powerdown input. In this mode, Interrupts will be asserted low using
this pin. Register access is required for the pin to be used as an interrupt
mechanism. See Section 5.8.2 for more details on the interrupt
mechanisms.
16 Pin Descriptions Copyright © 2007–2013, Texas Instruments Incorporated
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