Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
3.3 Serial Management Interface (SMI)
Signal Name Pin Name Type Pin # Description
MDC MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asynchronous
to transmit and receive clocks. The maximum clock rate is 25 MHz with no
minimum clock rate.
MDIO MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data
signal that may be sourced by the station management entity or the PHY.
This pin requires a 1.5 kΩ pullup resistor. Alternately, an internal pullup may
be enabled by setting bit 3 in the CDCTRL1 register.
3.4 MAC Data Interface
Signal Name Pin Name Type Pin # Description
TX_CLK TX_CLK O 1 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode
or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. The
MAC should source TX_EN and TXD[3:0] using this clock.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
TX_EN TX_EN I, PD 2 MII TRANSMIT ENABLE: Active high input indicates the presence of valid
data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid
data on TXD[1:0].
TXD_0 TXD_0 I 3 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept
TXD_1 TXD_1 I 4 data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in
TXD_2 TXD_2 I 5 100 Mb/s mode).
TXD_3 TXD_3 I, PD 6 RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that
accept data synchronous to the 50 MHz reference clock.
RX_CLK RX_CLK O 38 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for
100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RX_DV RX_DV O, PD 39 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: This signal provides the RMII Receive Data
Valid indication independent of Carrier Sense.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RX_ER RX_ER S, O, PU 41 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate
that an invalid symbol has been detected within a received packet in 100
Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a
media error is detected, and RX_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in RMII mode, since the PHY
is required to corrupt data on a receive error.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
RXD_0 RXD_0 S, O, PD 46 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously
RXD_1 RXD_1 45 to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode).
RXD_2 RXD_2 44 RXD[3:0] signals contain valid data when RX_DV is asserted.
RXD_3 RXD_3 43 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the 50 MHz reference clock.
These pins provide integrated 50 ohm signal terminations, making external
termination resistors unnecessary.
14 Pin Descriptions Copyright © 2007–2013, Texas Instruments Incorporated
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