Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
10.7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6
This register provides configuration for the reference clock source driving the IEEE 1588 logic. The source
clock period is also used by the 1588 clock nanoseconds adder to add the proper value every reference
clock cycle.
Table 10-71. PTP Clock Source Register (PTP_CLKSRC), address 0x1B
Bit Bit Name Default Description
15:1 CLK_SRC 00, RW PTP Clock Source Select:
4 Selects among three possible sources for the PTP reference clock:
00 : 125 MHz from internal PGM (default)
01 : Divide-by-N from 125 MHz internal PGM
1x : External reference clock
13:7 RESERVED 00 0000 0, RO Reserved: Writes ignored, Read as 0
6:0 CLK_SRC_PER 000 0000, RW PTP Clock Source Period:
This field configures the PTP clock source period in nanoseconds. Values less than
8 are invalid and cannot be written; attempting to write a value less than 8 will cause
CLK_SRC_PER to be 8. When the clock source selection is the Divide-by-N from
the internal PGM, bits 6:3 are used as the N value; bits 2:0 are ignored in this mode.
10.7.9 PTP Ethernet Type Register (PTP_ETR), Page 6
This register provides the Ethernet Type (Ethertype) field for PTP transport over Ethernet (Layer2).
Table 10-72. PTP Ethernet Type Register (PTP_ETR), address 0x1C
Bit Bit Name Default Description
15:0 PTP_ETYPE 1111 0111 1000 PTP Ethernet Type:
1000, RW This field contains the Ethernet Type field used to detect PTP messages transported
over Ethernet layer 2.
10.7.10 PTP Offset Register (PTP_OFF), Page 6
This register provides the byte offset to the PTP message in a Layer2 Ethernet frame.
Table 10-73. PTP Offset Register (PTP_OFF), address 0x1D
Bit Bit Name Default Description
15:8 RESERVED 0000 0000, RO Reserved: Writes ignored, Read as 0
7:0 PTP_OFFSET 0000 0000, RO PTP Offset:
This field contains the offset in bytes to the PTP Message from the preceding
header. For Layer2, this is the offset from the Ethernet Type Field. For UDP/IP, it is
the offset from the end of the UDP Header.
10.7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6
This register provides read-only access to the current values on GPIO inputs.
Table 10-74. PTP GPIO Monitor Register (PTP_GPIOMON), address 0x1E
Bit Bit Name Default Description
15:1 RESERVED 0000, RO Reserved: Writes ignored, Read as 0
2
11:0 PTP_GPIO_IN 0000 0000 0000, PTP GPIO Inputs:
RO This field reflects the current values seen on the GPIO inputs. GPIOs 12 through 1
are mapped to bits 11:0 in order.
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 129
Submit Documentation Feedback
Product Folder Links: DP83640