Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Table 10-62. PTP Temporary Rate Duration Low Register (PTP_TRDL), address 0x1E
Bit Bit Name Default Description
15:0 PTP_TR_DURL 0000 0000 0000 PTP Temporary Rate Duration Low 16 bits:
0000, RW This register sets the duration for the Temporary Rate in number of clock cycles.
The actual Time duration is dependent on the value of the Temporary Rate.
10.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5
This register contains the high 10 bits of the duration in clock cycles to use the Temporary Rate as
programmed in the PTP_RATEH and PTP_RATEL registers. Since the Temporary Rate takes affect upon
writing the PTP_RATEL register, this register should be programmed before setting the Temporary Rate.
This register does not need to be reprogrammed for each use of the Temporary Rate registers.
Table 10-63. PTP Temporary Rate Duration High Register (PTP_TRDH), address 0x1F
Bit Bit Name Default Description
15:1 RESERVED 0000 00, RO Reserved: Writes ignored, Read as 0
0
9:0 PTP_TR_DURH 00 0000 0000, RW PTP Temporary Rate Duration High 10 bits:
This register sets the duration for the Temporary Rate in number of clock cycles.
The actual Time duration is dependent on the value of the Temporary Rate.
126 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
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