Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
10.5.5 PTP Rate Low Register (PTP_RATEL), Page 4
This register contains the low 16-bits of the PTP Rate control. The PTP Rate Control indicates a positive
or negative adjustment to the reference clock period in units of 2
-32
ns. On each reference clock cycle, the
PTP Clock will be adjusted by adding REF_CLK_PERIOD +/- PTP_RATE. The PTP Rate should be
written as PTP_RATEH, followed by PTP_RATEL. The rate will take effect on the write to the
PTP_RATEL register.
Table 10-43. PTP Rate Low Register (PTP_RATEL), address 0x18
Bit Bit Name Default Description
15:0 PTP_RATE_LO 0000 0000 0000 PTP Rate Low 16-bits:
0000, RW Writing to this register will set the low 16-bits of the Rate Control value. The Rate
Control value is in units of 2
-32
ns. Upon writing to this register, the full Rate Control
value will be loaded to the device.
10.5.6 PTP Rate High Register (PTP_RATEH), Page 4
This register contains the upper bits of the PTP Rate control. In addition, it contains a direction control to
indicate whether the device is operating faster or slower than the reference clock frequency. When setting
the PTP Rate, this register should be written first, followed by a write to the PTP_RATEL register. The rate
will take effect on the write to the PTP_RATEL register.
Table 10-44. PTP Rate High Register (PTP_RATEH), address 0x19
Bit Bit Name Default Description
15 PTP_RATE_DIR 0, RW PTP Rate Direction:
The setting of this bit controls whether the device will operate at a higher or lower
frequency than the reference clock.
0 : Higher Frequency. The PTP_RATE value will be added to the clock on every
cycle.
1 : Lower Frequency. The PTP_RATE value will be subtracted from the clock on
every cycle.
14 PTP_TMP_RATE 0, RW PTP Temporary Rate:
Setting this bit will cause the rate to be applied to the clock for the duration set in the
PTP Temporary Rate Duration Register (PTP_TRD).
1 : Temporary Rate
0 : Normal Rate
13:1 RESERVED 00 00, RO Reserved: Writes ignored, Read as 0
0
9:0 PTP_RATE_HI 00 0000 0000, RW PTP Rate High 10-bits:
Writing to this register will set the high 10-bits of the Rate Control value. The Rate
Control value is in units of 2
-32
ns.
10.5.7 PTP Read Checksum (PTP_RDCKSUM), Page 4
This register keeps a running one’s complement checksum of 16-bit read data values for valid Page 4
read accesses. Clear the checksum on a read to this register; read data from this register is not
accumulated in the read checksum since the register is cleared on read. However, read data from the
write checksum register is accumulated to allow cross checking. Checksums are not accumulated for PHY
Control Frame register accesses, but are cleared on management or PHY Control Frame reads.
Table 10-45. PTP Read Checksum (PTP_RDCKSUM), address 0x1A
Bit Bit Name Default Description
15:0 RD_CKSUM XXXX XXXX XXXX PTP Read Checksum.
XXXX, RO/ COR
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 115
Submit Documentation Feedback
Product Folder Links: DP83640