Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
10.5.2 PTP Time Data Register (PTP_TDR), Page 4
This register provides a mechanism for reading and writing the 1588 Time and Trigger Control values. The
function of this register is determined by controls in the PTP_CTL register.
Table 10-40. PTP Time Data Register (PTP_TDR), address 0x15
Bit Bit Name Default Description
15:0 TIME_DATA XXXX XXXX XXXX Time Data:
XXXX, RO On Reads, successively returns 16-bit values of the Clock time or Trigger Control
XXXX XXXX XXXX information as selected by controls in the PTP Control Register. Additional reads
XXXX, WO beyond the avaliable fields will always return 0.
On Writes, successively stores the 16-bit values of Clock time or Trigger Control
Information as selected by controls in the PTP Control Register.
10.5.3 PTP Status Register (PTP_STS), Page 4
This register provides basic status and interrupt control for the PTP 1588 operation.
Table 10-41. PTP Status Register (PTP_STS), address 0x16
Bit Bit Name Default Description
15:1 RESERVED 0000, RO Reserved: Writes ignored, Read as 0
2
11 TXTS_RDY 0, RO Transmit Timestamp Ready:
A Transmit Timestamp is available for an outbound PTP Message. This bit will be
cleared upon read of the Transmit Timestamp if no other timestamps are ready.
10 RXTS_RDY 0, RO Receive Timestamp Ready:
A Receive Timestamp is available for an inbound PTP Message. This bit will be
cleared upon read of the Receive Timestamp if no other timestamps are ready.
9 TRIG_DONE 0, RO/COR PTP Trigger Done:
A PTP Trigger has occured. This bit will be cleared upon read. This bit will only be
set if Trigger Notification is turned on for the Trigger through the Trigger
Configuration Registers.
8 EVENT_RDY 0, RO PTP Event Timestamp Ready:
A PTP Event Timestamp is available. This bit will be cleared upon read of the PTP
Event Status Register if no other event timestamps are ready.
7:4 RESERVED 0000, RO Reserved: Writes ignored, Read as 0
3 TXTS_IE 0, RW Transmit Timestamp Interrupt Enable:
Enable Interrupt on Transmit Timestamp Ready.
2 RXTS_IE 0, RW Receive Timestamp Interrupt Enable:
Enable Interrupt on Receive Timestamp Ready.
1 TRIG_IE 0, RW Trigger Interrupt Enable:
Enable Interrupt on Trigger Completion.
0 EVENT_IE 0, RW Event Interrupt Enable:
Enable Interrupt on Event Timestamp Ready.
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 113
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