Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
10.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2
This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor
provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are
violated, an interrupt will be asserted if enabled in the MISR. Monitor control and status are available in
this register, while the LQDR register controls read/write access to threshold values and current parameter
values. Reading of LQMR2 register clears its warning bits but does NOT re-arm the interrupt generation;
LQMR must be read to re-arm interrupt generation. In addition, this register provides a mechanism for
allowing automatic reset of the 100 Mb link based on the Link Quality Monitor variance status.
Table 10-38. Link Quality Monitor Register 2 (LQMR2), address 0x1F
Bit Bit Name Default Description
15:1 RESERVED 0000 0, RO Reserved: Writes ignored, Read as 0
1
10 RESTART_ON_VAR 0, RW Restart on Variance Warning:
Allow automatic reset of DSP and restart of 100 Mb Adaption on detecting a
Frequency Offset Threshold violation. If the SD_Option bit, PCSR[8], is set to 0, the
threshold violation will also result in a drop in Link status.
9:2 RESERVED 00 0000 00, RO Reserved: Writes ignored, Read as 0
1 VAR_HI_WARN 0, RO/COR Variance High Warning:
This bit indicates the Variance High Threshold was exceeded. This register bit will
be cleared on read.
0 RESERVED 0, RO Reserved: Writes ignored, Read as 0
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