Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Table 10-22. 10Base-T Status/Control Register (10BTSCR), address 0x1A (continued)
Bit Bit Name Default Description
3 AUTOPOL_DIS 0, RW Auto Polarity Detection & Correction Disable:
1 = Polarity Correction disabled
0 = Polarity Correction enabled
2 10BT_SCALE - MSB 1, RW 10BT Scale Configuration Most Significant Bit
Used in conjunction with bit 10 of SD_CNFG register to set the silence ’OFF’
threshold for the receiver.
1 HEARTBEAT_DIS 0, RW Heartbeat Disable:
This bit only has influence in half-duplex 10 Mb mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100 Mb or configured for full duplex
operation, this bit will be ignored - the heartbeat function is disabled.
0 JABBER_DIS 0, RW Jabber Disable:
This bit is only applicable in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
10.2.8 CD Test and BIST Extensions Register (CDCTRL1)
This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended
control and status for the packet BIST function.
Table 10-23. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B
Bit Bit Name Default Description
15:8 BIST_ERROR_COUNT 0000 0000, RO BIST ERROR Counter:
Counts number of errored data nibbles during Packet BIST. This value
will reset when Packet BIST is restarted. The counter sticks when it
reaches its maximum count of FFh.
7 RESERVED 0, RW RESERVED: Must be 0.
6 MII_CLOCK_EN 0, RW Enables MII Clocks TX_CLK and RX_CLK independent of MAC interface
mode selected; for example, normally TX_CLK and RX_CLK are
disabled in RMII Slave mode.
1 = Enable TX_CLK and RX_CLK
0 = Default operation
5 BIST_CONT 0, RW Packet BIST Continuous Mode:
Allows continuous pseudorandom data transmission without any break in
transmission. This can be used for transmit VOD testing. This is used in
conjunction with the BIST controls in the PHYCR Register (19h). For 10
Mb operation, jabber function must be disabled, bit 0 of the 10BTSCR
(1Ah), JABBER_DIS = 1.
4 CDPATTEN_10 0, RW CD Pattern Enable for 10 Mb:
1 = Enabled.
0 = Disabled.
3 MDIO_PULL_EN 0, RW Enable Internal MDIO Pullup:
1 = Internal MDIO pullup enabled
0 = Internal MDIO pullup disabled
This bit is only reset on hard reset. This bit should not be set in systems
that share the management interfaces among several ASICs.
2 PATT_GAP_10M 0, RW Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
100 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
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