Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Table 10-14. MII Interrupt Status and Event Control Register (MISR), address 0x12 (continued)
Bit Bit Name Default Description
8 RHF_INT 0, RO/COR Receive Error Counter half-full interrupt:
or Receive error counter half-full interrupt. This function is selected if the
PCF_INT PHYCR2[8:7] are both 0.
1 = Receive error counter half-full interrupt is pending and is cleared by the current
read.
0 = No receive error carrier counter half-full interrupt pending.
PCF Interrupt:
PHY Control Frame interrupt. This function is selected if either of PHYCR2[8:7] are
set.
1 = PHY Control Frame interrupt is pending and is cleared by the current read.
0 = No PHY Control Frame interrupt pending.
7 LQ_INT_EN 0, RW Enable Interrupt on Link Quality Monitor event.
6 ED_INT_EN 0, RW Enable Interrupt on energy detect event.
5 LINK_INT_EN 0, RW Enable Interrupt on change of link status.
4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status.
3 DUP_INT_EN 0, RW Duplex Interrupt:
or Enable Interrupt on change of duplex status. This function is selected if MICR[3] is
PTP_INT_EN set to 0.
PTP Interrupt:
PTP interrupt. This function is selected if MICR[3] is set to 1.
2 ANC_INT_EN 0, RW Enable Interrupt on auto-negotiation complete event.
1 FHF_INT_EN 0, RW FHF Interrupt:
or Enable Interrupt on False Carrier Counter Register halffull event. This function is
CTR_INT_EN selected if the PHYCR2[8:7] are both 0.
CTR Interrupt:
Enable interrupt on either Receive Error Counter Register half-full event or False
Carrier Counter Register half-full event. This function is selected if either of
PCFCR[7:6] are set.
0 RHF_INT_EN 0, RW RHF Interrupt:
or Enable Interrupt on Receive Error Counter Register halffull event. This function is
PCF_INT_EN selected if the PHYCR2[8:7] are both 0.
PCF Interrupt:
Enable Interrupt on a PHY Control Frame event. This function is selected if either
of PCFCR[7:6] are set.
10.1.13 Page Select Register (PAGESEL)
This register is used to enable access to the Link Diagnostics Registers.
Table 10-15. Page Select Register (PAGESEL), address 0x13
Bit Bit Name Default Description
15:3 RESERVED 0000 0000 0000 0, RESERVED: Writes ignored, read as 0
RO
2:0 PAGE_SEL 000, RW Page_Sel Bits:
Selects between paged registers for address 14h to 1Fh.
0 = Extended Registers Page 0
1 = RESERVED
2 = Link Diagnostics Registers Page 2
3 = RESERVED
4 = PTP 1588 Base Registers Page 4
5 = PTP 1588 Config Registers Page 5
6 = PTP 1588 Config Registers Page 6
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