Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Table 10-2. Register Table (continued)
Register Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
PTP Event 15h PTP_EV Reserve EVNT_R EVNT_F Reserve EVNT_ EVNT_ EVNT_ EVNT_ Reserve Reserve Reserved Reserve EVNT_SE EVNT_S EVNT_SE EVNT_
Configuration NT d ISE ALL d GPIO GPIO GPIO GPIO d d d L EL L WR
Register
PTP Transmit 16h PTP_TX SYNC_1 Reserve DR_INS Reserve RESER CRC_1S CHK_1S IP1588_ TX_L2_ TX_IPV TX_IPV4_ TX_PTP TX_PTP_ TX_PTP TX_PTP_ TX_TS_
Configuration CFG0 STEP d ERT d VED_1 TEP TEP EN EN 6_EN EN _VER VER _VER VER EN
Register 0
PTP Transmit 17h PTP_TX BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_D BYTE0_ BYTE0_D BYTE0_ BYTE0_D BYTE0_
Configuration CFG1 MASK MASK MASK MASK MASK MASK MASK MASK DATA DATA ATA DATA ATA DATA ATA DATA
Register 1
PHY Status 18h PSF_CF Reserve Reserve Reserve MAC_S MAC_S MIN_PR MIN_PR MIN_PR PSF_EN PSF_IP PSF_PCF PSF_ER PSF_TXT PSF_RX PSF_TRIG PSF_EV
Frame G0 d d d RC_AD RC_AD E E E DIAN V4 _RD R_EN S_EN TS_EN _EN NT_EN
Configuration D D
Register 0
PTP Receive 19h PTP_RX DOMAI Reserve USER_I USER_I RX_SLA IP1588_ IP1588_ IP1588_ RX_L2_ RX_IPV RX_IPV4_ RX_PTP RX_PTP_ RX_PTP RX_PTP_ RX_TS_
Configuration CFG0 N_EN d P_SEL P_EN VE EN EN EN EN 6_EN EN _VER VER _VER VER EN
Register 0
PTP Receive 1Ah PTP_RX BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_ BYTE0_D BYTE0_ BYTE0_D BYTE0_ BYTE0_D BYTE0_
Configuration CFG1 MASK MASK MASK MASK MASK MASK MASK MASK DATA DATA ATA DATA ATA DATA ATA DATA
Register 1
PTP Receive 1Bh PTP_RX IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADD IP_ADDR_ IP_ADD IP_ADDR_ IP_ADD IP_ADDR_ IP_ADD
Configuration CFG2 R_DATA R_DATA R_DATA R_DATA R_DATA R_DATA R_DATA R_DATA R_DATA R_DATA DATA R_DATA DATA R_DATA DATA R_DATA
Register 2
PTP Receive 1Ch PTP_RX TS_MIN TS_MIN TS_MIN TS_MIN ACC_U ACC_C TS_APP TS_INS PTP_D PTP_D PTP_DOM PTP_D PTP_DOM PTP_D PTP_DOM PTP_D
Configuration CFG3 _IFG _IFG _IFG _IFG DP RC END ERT OMAIN OMAIN AIN OMAIN AIN OMAIN AIN OMAIN
Register 3
PTP Receive 1Dh PTP_RX IPV4_U TS_SEC TS_SEC TS_SEC RXTS_N RXTS_N RXTS_N RXTS_N RXTS_N RXTS_N RXTS_SE RXTS_S RXTS_SE RXTS_S RXTS_SE RXTS_S
Configuration CFG4 DP_MO _EN _LEN _LEN S_OFF S_OFF S_OFF S_OFF S_OFF S_OFF C_OFF EC_OFF C_OFF EC_OFF C_OFF EC_OFF
Register 4 D
PTP 1Eh PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR_ PTP_TR PTP_TR_ PTP_TR PTP_TR_ PTP_TR
Temporary DL _DURL _DURL _DURL _DURL _DURL _DURL _DURL _DURL _DURL _DURL DURL _DURL DURL _DURL DURL _DURL
Rate Duration
Low Register
PTP 1Fh PTP_TR Reserve Reserve Reserve Reserve Reserve Reserve PTP_TR PTP_TR PTP_TR PTP_TR PTP_TR_ PTP_TR PTP_TR_ PTP_TR PTP_TR_ PTP_TR
Temporary DH d d d d d d _DURH _DURH _DURH _DURH DURH _DURH DURH _DURH DURH _DURH
Rate Duration
High Register
PTP 1588 CONFIGURATION REGISTERS - PAGE 6
PTP Clock 14h PTP_C PTP_CL PTP_CL PTP_CL Reserve Reserve Reserve Reserve Reserve PTP_CL PTP_CL PTP_CLK PTP_CL PTP_CLK PTP_CL PTP_CLK PTP_CL
Output Control OC KOUT KOUT KOUT d d d d d KDIV KDIV DIV KDIV DIV KDIV DIV KDIV
Register EN SEL SPEED
SEL
PHY Status 15h PSF_CF PTPRE PTPRE PTPRE PTPRE VERSIO VERSIO VERSIO VERSIO TRANS TRANS TRANSPO TRANS MESSAGE MESSA MESSAGE MESSA
Frame G1 SERVE SERVE SERVE SERVE NPTP NPTP NPTP NPTP PORTS PORTS RTSPECIF PORTS TYPE GETYP TYPE GETYP
Configuration D D D D PECIFIC PECIFIC IC PECIFIC E E
Register 1
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 81
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