Datasheet
DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
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Table 10-2. Register Table (continued)
Register Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
MII Interrupt 12h MISR LQ_INT ED_INT LINK_IN SPD_IN DUP_IN ANC_IN FHF_IN RHF_IN LQ_INT ED_INT LINK_INT_ SPED_I DUP_INT_ ANC_IN FHF_INT_ RHF_IN
Status and T T T T T T _EN _EN EN NT_EN EN T_EN EN T_EN
Misc. Control or or or or or or
Register SPD_D PTP_IN CTR_IN PCF_IN CTR_INT_ PCF_IN
UP_INT T T T EN T_EN
Page Select 13h Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserved Reserve Reserved Page_S Page_Sel Page_S
Register d d d d d d d d d d d d el Bit Bit el Bit
EXTENDED REGISTERS - PAGE 0
False Carrier 14h FCSCR Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve FCSCN FCSCN FCSCNT FCSCN FCSCNT FCSCN FCSCNT FCSCN
Sense Counter d d d d d d d d T T T T T
Register
Receive Error 15h RECR Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve RXERC RXERC RXERCNT RXERC RXERCNT RXERC RXERCNT RXERC
Counter d d d d d d d d NT NT NT NT NT
Register
PCS Sub- 16h PCSR Reserve Reserve Reserve Reserve FREE_C TQ_EN SD_FO SD_ DESC_T FX_EN FORCE_ Reserve FEFI_EN NRZI_ SCRAM_ DE
Layer d d d d LK RCE_P IME d
OPTION 100_OK BYPAS BYPASS SCRAM
Configuration MA
S _BYPAS
and Status
S
Register
RMII and 17h RBR Reserve RMII_M DIS_TX RX_PO RX_PO TX_SO TX_SO PMD_L SCMII_ SCMII_T RMII_MO RMII_R RX_OVF_ RX_UN ELAST_B ELAST_
Bypass d ASTER _OPT RT RT URCE URCE OOP RX X DE EV1_0 STS F_STS UF BUF
Register
LED Direct 18h LEDCR Reserve Reserve Reserve Reserve DIS_SP DIS_LN DIS_AC LEDACT BLINK_ BLINK_ DRV_SPD DRV_LN DRV_ACT SPDLE LNKLED ACTLED
Control d d d d DLED KLED TLED _RX FREQ FREQ LED KLED LED D
Register
PHY Control 19h PHYCR MDIX_E FORCE PAUSE_ PAUSE_ BIST_F PSR_15 BIST_ BIST_S BP_STR LED_ LED_ PHY PHY PHY PHY PHY
Register N _MDIX RX TX E TART ETCH
STATUS CNFG[1] CNFG[0] ADDR ADDR ADDR ADDR ADDR
10Base-T 1Ah 10BTSC Reserve Reserve Reserve Reserve SQUEL SQUEL SQUEL LOOPB LP_DIS FORCE FORCE_P POLARI AUTOPOL 10BT_S HEARTBE JABBER
Status/Control R d d d d CH CH CH ACK_10 _ OL COR TY _DIS CALE_ AT_DIS _DIS
Register _DIS MSB
LINK_10
CD Test 1Bh CDCTR BIST_E BIST_E BIST_E BIST_E BIST_E BIST_E BIST_E BIST_E Reserve MII_CL BIST_CO CDPAT MDIO_PU PATT_G CDPATTS CDPAT
Control and L1 RROR_ RROR_ RROR_ RROR_ RROR_ RROR_ RROR_ RROR_ d OCK_E NT TEN_10 LL_EN AP_10M EL TSEL
BIST COUNT COUNT COUNT COUNT COUNT COUNT COUNT COUNT N
Extensions
Register
PHY Control 1Ch PHYCR Reserve Reserve SYNC_ CLK_O BC_WRI PHYTE SOFT_R Reserve Reserve Reserve Reserved Reserve Reserved Reserve CLK_OUT Reserve
Register 2 2 d d ENET_E UT TE R_COM ESET d d d d d _DIS d
N RXCLK P
Energy Detect 1Dh EDCR ED_EN ED_AUT ED_AUT ED_MA ED_BU ED_PW ED_ER ED_DAT ED_ER ED_ER ED_ERR_ ED_ER ED_DATA ED_DAT ED_DATA ED_DAT
Control O_UP O_DOW N RST_DI R_STAT R_MET A_MET R_COU R_COU COUNT R_COU _COUNT A_COU _COUNT A_COU
Register N S E NT NT NT NT NT
RESERVED 1Eh Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserved Reserve Reserved Reserve Reserved Reserve
d d d d d d d d d d d d d d
78 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
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