Datasheet

DP83640

SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013

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7.2.2.2 Digital Adaptive Equalization and Gain Control

The DP83640 utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’

The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously

adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined

with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to

allow very reliable data recovery.

7.2.3 Signal Detect

The signal detect function of the DP83640 is incorporated to meet the specifications mandated by the

ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage

thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-

Negotiation by the 100BASE-TX receiver do not cause the DP83640 to assert signal detect.

7.2.4 MLT-3 to Binary Decoder

The DP83640 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI

data.

7.2.5 Clock Recovery Module

The Clock Recovery function is implemented as a Phase detector and Loop Filter which accepts data and

error from the receive datapath to detect the phase of the recovered data. This phase information is fed

into the loop filter to determine an 8-bit signed frequency control. The 8-bit signed frequency control is

sent to the FCO in the Analog Front End to derive the receive clock. The extracted and synchronized

clock and data are used as required by the synchronous receive operations as generally depicted in

Figure 7-2.

7.2.6 NRZI to NRZ Decoder

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the

descrambler (or to the code-group alignment block if the descrambler is bypassed).

7.2.7 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols

to the PCS Rx state machine.

7.2.8 Descrambler

A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an

identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the

scrambled data (SD) as represented in the equations:

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the

knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the

descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group

in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and

generate unscrambled data in the form of unaligned 5B code-groups.

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