Datasheet

4B/5B DECODER
SERIAL TO
PARALLEL
CODE GROUP
ALIGNMENT
DESCRAMBLER
NRZI TO NRZ
DECODER
MLT-3 TO BINARY
DECODER
DIGITAL
ADAPTIVE
EQUALIZATION
AUTOMATIC GAIN
CONTROL
ANALOG
ADAPTATION
CONTROL
CLOCK
RECOVERY
(LOOPFILTER)
INPUT BLW
COMPENSATION
ADC Data
RD +/-
RXD[3:0] / RX_ER
AFE
ANALOG
AGC
ANALOG
EQUALIZER
FCO
SIGNAL DETECT
CLOCK
RECOVERY
MODULE
LINK INTEGRITY
MONITOR
DIVIDE BY 5
MUX
RX_DATA VALID
SSD DETECT
BP_SCR
RX_CLKRX_DV/CRS
CLOCK
DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Figure 7-2. 100BASE-TX Receive Block Diagram
7.2.2.1 Base Line Wander Compensation
The DP83640 is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW)
compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer”
pattern.
Copyright © 2007–2013, Texas Instruments Incorporated Architecture 63
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