Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
5.10.1.2 Cable Swap Indication
As part of Auto-Negotiation, the DP83640 has the ability (using Auto-MDIX) to automatically detect a cable
with swapped MDI pairs and select the appropriate pairs for transmitting and receiving data. Normal
operation is termed MDI, while crossed operation is MDIX. The MDIX status can be read from bit 14 of the
PHYSTS (10h).
5.10.1.3 100 Mb Cable Length Estimation
The DP83640 provides a method of estimating cable length based on electrical characteristics of the 100
Mb link. This essentially provides an effective cable length rather than a measurement of the physical
cable length. The cable length estimation is only available in 100 Mb mode of operation with a valid link
status. The cable length estimation is available at the Link Diagnostics Registers - Page 2, register 100
Mb Length Detect (LEN100_DET), address 14h.
5.10.1.4 Frequency Offset Relative to Link Partner
As part of the 100 Mb clock recovery process, the DSP implementation provides a frequency control
parameter. This value may be used to indicate the frequency offset of the device relative to the link
partner. This operation is only available in 100 Mb operation with a valid link status. The frequency offset
can be determined using the register 100 Mb Frequency Offset Indication (FREQ100), address 15h, of the
Link Diagnostics Registers - Page 2.
Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100
(15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value,
which includes short-term phase adjustments and can provide information on the amount of jitter in the
system.
5.10.1.5 Cable Signal Quality Estimation
The cable signal quality estimator keeps a simple tracking of results of the DSP and can be used to
generate an approximate Signal-to-Noise Ratio for the 100 Mb receiver. This information is available to
software through the Link Diagnostics Registers - Page 2: Variance Control Register (VAR_CTRL),
address 1Ah and Variance Data Register (VAR_DATA), address 1Bh.
The variance computation times (VAR_TIMER) can be chosen from the set of {2, 4, 6, 8} ms. The 32-bit
variance sum can be read by two consecutive reads of the VAR_DATA register. This sum can be used to
compute an SNR estimate by software using the following equation:
SNR = 10log
10
((37748736 * VAR_TIMER) / Variance).
5.10.2 Link Quality Monitor
The Link Quality Monitor allows a method to generate an alarm when the DSP adaption strays from a
programmable window. This could occur due to changes in the cable which could indicate a potential
problem. Software can program thresholds for the following DSP parameters to be used to interrupt the
system:
• Digital Equalizer C1 Coefficient (DEQ C1)
• Digital Adaptive Gain Control (DAGC)
• Digital Base-Line Wander Control (DBLW)
• Recovered Clock Long-Term Frequency Offset (FREQ)
• Recovered Clock Frequency Control (FC)
• Signal-to-Noise Ratio (SNR) Variance
Software is expected to read initial adapted values and then program the thresholds based on an
expected valid range. This mechanism takes advantage of the fact that the DSP adaptation should remain
in a relatively small range once a valid link has been established.
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