Datasheet

T2.32.1
TX_CLK
X1
DataIDLE Data(J/K) (TR)
T2.31.4
T2.31.1
T2.31.5
T2.31.3
T2.31.2
T2.31.2
PMD Input
Pair
X1
CRS/CSR_DV
RX_DV
RXD[3:0]
RX_ER
DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
4.35 AC Specifications — Single Clock MII (SCMII) Receive Timing
Parameter Description Notes Min Typ Max Units
T2.31.1 X1 Clock Period 25 MHz Reference Clock
(1)
40 ns
T2.31.2 RXD[3:0], RX_DV and RX_ER output From X1 rising edge 2 18 ns
delay
(2)
T2.31.3 CRS ON delay
(3)
100BASE-TX mode 19 bits
100BASE-FX mode 9
T2.31.4 CRS OFF delay
(4)
100BASE-TX mode 26 bits
100BASE-FX mode 16
T2.31.5 RXD[3:0] and RX_ER latency
(5)
100BASE-TX mode 56 bits
100BASE-FX mode 46
(1) CRS is asserted and de-asserted asynchronously relative to the reference clock.
(2) Output delays assume a 25 pF load.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
Figure 4-31. Single Clock MII (SCMII) Receive Timing
4.36 AC Specifications — 100 Mb/s X1 to TX_CLK Timing
Parameter Description Notes Min Typ Max Units
T2.32.1 X1 to TX_CLK delay
(1)
100 Mb/s Normal mode 0 5 ns
(1) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data.
Figure 4-32. 100 Mb/s X1 to TX_CLK Timing
Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 39
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