Datasheet

RX_CLK
T2.28.1 T2.28.2
T2.28.3
RX_CLK
TX_CLK
CLK_OUT
DataIDLE Data(J/K) (TR)
T2.27.4
T2.27.1
T2.27.5
T2.27.3
T2.27.2
T2.27.2
T2.27.2
T2.27.2
PMD Input
Pair
RX_DV
CRS/CRS_DV
RXD[1:0]
RX_ER
DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
4.31 AC Specifications — RMII Receive Timing (Master Mode)
Parameter Description
(1)
Notes Min Typ Max Units
T2.27.1 RX_CLK, TX_CLK, CLK_OUT 50 MHz Reference Clock 20 ns
Clock Period
T2.27.2 RXD[1:0], CRS_DV, RX_DV and 2 14 ns
RX_ER output delay from
RX_CLK, TX_CLK, CLK_OUT
rising edge
(2)
T2.27.3 CRS ON delay
(3)
100BASE-TX mode 18.5 bits
100BASE-FX mode 9
T2.27.4 CRS OFF delay
(4)
100BASE-TX mode 27 bits
100BASE-FX mode 17
T2.27.5 RXD[1:0] and RX_ER latency
(5)
100BASE-TX mode 38 bits
100BASE-FX mode 27
(1) Per the RMII Specification, output delays assume a 25 pF load.
(2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS de-assertion.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
Figure 4-27. RMII Receive Timing (Master Mode)
4.32 AC Specifications — RX_CLK Timing (RMII Master Mode)
Parameter Description Notes Min Typ Max Units
T2.28.1 RX_CLK High Time
(1)
12 ns
T2.28.2 RX_CLK Low Time
(1)
8 ns
T2.28.3 RX_CLK Period 20 ns
(1) The High Time and Low Tme will add up to 20 ns.
Figure 4-28. RX_CLK Timing (RMII Master Mode)
Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 37
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