Datasheet

PMD Input
Pair
SD+ internal
T2.21.1 T2.21.2
T.2.20.2
T2.20.1
Fast Link
Pulse(s)
T2.20.1
T2.20.3
clock
pulse
data
pulse
clock
pulse
FLP Burst FLP Burst
T2.20.5
T2.20.4
PMD
Output Pair
DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
4.24 AC Specifications — Auto-Negotiation Fast Link Pulse (FLP) Timing
Parameter Description Notes Min Typ
(1)
Max Units
T2.20.1 Clock, Data Pulse Width 100 ns
T2.20.2 Clock Pulse to Clock Pulse 125 µs
Period
T2.20.3 Clock Pulse to Data Pulse Data = 1 62 µs
Period
T2.20.4 Burst Width 2 ms
T2.20.5 FLP Burst to FLP Burst Period 16 ms
(1) These specifications represent transmit timings
Figure 4-20. Auto-Negotiation Fast Link Pulse (FLP) Timing
4.25 AC Specifications — 100BASE-TX Signal Detect Timing
Parameter Description
(1)
Notes Min Typ Max Units
T2.21.1 SD Internal Turn-on Time 1 ms
T2.21.2 SD Internal Turn-off Time Default operation 250 300 µs
Fast link-loss indication 1.3 µs
enabled
(2)
(1) The signal amplitude on PMD Input Pair must be TP-PMD compliant.
(2) Fast Link-loss detect is enabled by setting the SD_CNFG[8] register bit to a 1.
Figure 4-21. 100BASE-TX Signal Detect Timing
Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 31
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