Datasheet

T2.12.1
T2.12.3T2.12.2
Valid Data
RX_CLK
RXD[3:0]
RX_DV
T2.12.1
T2.11.1 T2.11.1
T2.11.2
T2.11.3
Valid Data
TX_CLK
TXD[3:0]
TX_EN
DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
4.15 AC Specifications — 10 Mb/s MII Transmit Timing
Parameter Description
(1)
Notes Min Typ Max Units
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to 10 Mb/s MII mode 25 ns
TX_CLK falling edge
T2.11.3 TXD[3:0], TX_EN Data Hold from 10 Mb/s MII mode 0 ns
TX_CLK rising edge
(1) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
Figure 4-11. 10 Mb/s MII Transmit Timing
4.16 AC Specifications — 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.12.1 RX_CLK High/Low Time
(1)
160 200 240 ns
T2.12.2 RXD[3:0], RX_DV transition delay from 10 Mb/s MII mode 100 ns
RX_CLK rising edge
T2.12.3 RX_CLK rising edge delay from 10 Mb/s MII mode 100 ns
RXD[3:0], RX_DV valid data
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
Figure 4-12. 10 Mb/s MII Receive Timing
Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 27
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