Datasheet

IDLE(T/R)DATA
T2.10.1
CRS/CRS_DV
PMD Input Pair
Data(J/K)IDLE
T2.9.2
T2.9.1
CRS/CRS_DV
PMD Input Pair
RXD[3:0]
RX_DV
RX_ER
DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
4.13 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Latency
Timing
Parameter Description Notes Min Typ Max Units
(1)
T2.9.1 Carrier Sense ON Delay
(2)
100BASE-TX mode 20 bits
100BASE-FX mode 10
T2.9.2 Receive Data Latency
(3)(4)
100BASE-TX mode 24 bits
100BASE-FX mode 14
(1) 1 bit time = 10 ns in 100 Mb/s mode.
(2) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(3) Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.
(4) Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive
datapath.
Figure 4-9. 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing
4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion
Timing
Parameter Description Notes Min Typ Max Units
(1)
T2.10.1 Carrier Sense OFF Delay
(2)
100BASE-TX mode 24 bits
100BASE-FX mode 14
(1) 1 bit time = 10 ns in 100 Mb/s mode.
(2) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
Figure 4-10. 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing
26 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83640