Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
3.10 Strap Options
The DP83640 uses many of the functional pins as strap options to place the device into specific modes of
operation. The values of these pins are sampled at power up or hard reset. During software resets, the
strap options are internally reloaded from the values sampled at power up or hard reset. The strap option
pin assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to V
CC
or GND.
Signal Name Pin Name Type Pin # Description
PHYAD0 COL S, O, PU 42 PHY ADDRESS [4:0]: The DP83640 provides five PHY address pins,
PHYAD1 RXD_3 S, O, PD 43 the state of which are latched into the PHYCTRL register at system
PHYAD2 RXD_2 S, O, PD 44 Hardware-Reset.
PHYAD3 RXD_1 S, O, PD 45 The DP83640 supports PHY Address strapping values 0 (<00000>)
PHYAD4 RXD_0 S, O, PD 46 through 31 (<11111>).A PHY Address of 0 puts the part into the MII
Isolate Mode. The MII isolate mode must be selected by strapping
PHY Address 0; changing to Address 0 by register write will not put the
PHY in the MII isolate mode.
PHYAD[0] pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
AN_EN LED_LINK S, O, PU 28 AUTO-NEGOTIATION ENABLE: When high, this enables Auto-
AN1 LED_SPEED/FX_S S, O, PU 27 Negotiation with the capability set by AN0 and AN1 pins. When low, this
D puts the part into Forced Mode with the capability set by AN0 and AN1
AN0 LED_ACT S, O, PU 26 pins.
AN0 / AN1: These input pins control the forced or advertised operating
mode of the DP83640 according to the following table. The value on
these pins is set by connecting the input pins to GND (0) or V
CC
(1)
through 2.2 kΩ resistors. These pins should NEVER be connected
directly to GND or V
CC
.
The value set at this input is latched into the DP83640 at Hardware-
Reset.
The float/pull-down status of these pins are latched into the Basic Mode
Control Register and the Auto_Negotiation Advertisement Register
during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using
the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select
half or full duplex. AN_EN and AN1 are ignored in Fiber mode since it
is 100 Mb only and does not support Auto-Negotiation. In Fiber mode,
AN1 should not be connected to any system components except the
fiber transceiver.
FX_EN_ AN_EN AN1 AN0 Forced Mode
Z
1 0 0 0 10BASE-T, Half-Duplex
1 0 0 1 10BASE-T, Full-Duplex
1 0 1 0 100BASE-TX, Half-Duplex
1 0 1 1 100BASE-TX, Full-Duplex
0 X X 0 100BASE-FX, Half-Duplex
0 X X 1 100BASE-FX, Full-Duplex
FX_EN_ AN_EN AN1 AN0 Advertised Mode
Z
1 1 0 0 10BASE-T, Half/Full-Duplex
1 1 0 1 100BASE-TX, Half/Full-Duplex
1 1 1 0 100BASE-TX, Full-Duplex
1 1 1 1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
CLK_OUT_EN GPIO1 S, I, PD 21 CLK_OUT OUTPUT ENABLE: When high, enables clock output on the
CLK_OUT pin at power-up.
Copyright © 2007–2013, Texas Instruments Incorporated Pin Descriptions 17
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