Datasheet

DP83640
www.ti.com SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013
Table 10-53. PTP Event Configuration Register (PTP_EVNT), address 0x15 (continued)
Bit Bit Name Default Description
12 EVNT_SINGLE 0, RW Single Event Capture: Setting this bit to a 1 will enable single event capture
operation. The EVNT_RISE and EVNT_FALL enables will be cleared upon a valid
event timestamp capture.
11:8 EVNT_GPIO 0000, RW Event GPIO Connection:
Setting this field to a non-zero value will connect the Event to the associated GPIO
pin. Valid settings for this field are 1 thru 12.
7:4 RESERVED 0000, RO Reserved: Writes ignored, Read as 0
3:1 EVNT_SEL 000, RW Event Select:
This field selects the Event Timestamp Unit for configuration read or write.
0 EVNT_WR 0, RW Event Configuration Write:
Setting this bit will generate a Configuration Write to the selected Event Timestamp
Unit.
10.6.3 PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5
This register provides configuration for IEEE 1588 Transmit Timestamp operation.
Table 10-54. PTP Transmit Configuration Register 0 (PTP_TXCFG0), address 0x16
Bit Bit Name Default Description
15 SYNC_1STEP 0, RW Sync Message One-Step Enable:
Enable automatic insertion of timestamp into transmit Sync Messages. Device will
automatically parse message and insert the timestamp in the correct location. UPD
checksum and CRC fields will be regenerated.
14 RESERVED 0, RO Reserved: Writes ignored, Read as 0
13 DR_INSERT 0, RW Insert Delay_Req Timestamp in Delay_Resp:
If this bit is set to a 1, the device insert the timestamp for transmitted Delay_Req
messages into inbound Delay_Resp messages. The most recent timestamp will be
used for any inbound Delay_Resp message. The receive timestamp insertion logic
must be enabled through the PTP Receive Configuration Registers.
12 NTP_TS_EN 0, RW Enable Timestamping of NTP Packets:
If this bit is set to 0, the device will check the UDP protocol field for a PTP Event
message (value 319). If this bit is set to 1, the device will check the UDP protocol
field for an NTP message (value 123). This setting applies to the transmit and
receive packet parsing engines.
11 IGNORE_2STEP 0, RW Ignore Two_Step flag for One-Step operation:
If this bit is set to a 0, the device will not insert a timestamp if the Two_Step bit is set
in the flags field of the PTP header. If this bit is set to 1, the device will insert a
timestamp independent of the setting of the Two_Step flag.
10 CRC_1STEP 0, RW Disable checking of CRC for One-Step operation:
If this bit is set to a 0, the device will force a CRC error for One-Step operation if the
incoming frame has a CRC error. If this bit is set to a 1, the device will send the
One- Step frame with a valid CRC, even if the incoming CRC is invalid.
9 CHK_1STEP 0, RW Enable UDP Checksum correction for One-Step Operation:
Enables correction of the UDP checksum for messages which include insertion of
the timestamp. The checksum is corrected by modifying the last two bytes of the
UDP data. The last two bytes must be transmitted by the MAC as 0’s. This control
must be set for proper IPv6/UDP One-Step operation. This control will have no
effect for Layer2 Ethernet messages.
8 IP1588_EN 0, RW Enable IEEE 1588 defined IP address filter:
Enable filtering of UDP/IP Event messages using the IANA assigned IP Destination
addresses. If this bit is set to 1, packets with IP Destination addresses which do not
match the IANA assigned addresses will not be timestamped. This field affects
operation for both IPv4 and IPv6. If this field is set to 0, IP destination addresses will
be ignored.
7 TX_L2_EN 0, RW Layer2 Timestamp Enable:
Enables detection of IEEE 802.3/Ethernet encapsulated PTP event messages.
6 TX_IPV6_EN 0, RW IPv6 Timestamp Enable:
Enables detection of UDP/IPv6 encapsulated PTP event messages.
5 TX_IPV4_EN 0, RW IPv4 Timestamp Enable:
Enables detection of UDP/IPv4 encapsulated PTP event messages.
Copyright © 2007–2013, Texas Instruments Incorporated Register Block 121
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