Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
10.5 PTP 1588 Base Registers - Page 4
Page 4 PTP 1588 Base Registers are accessible by setting bits [2:0] = 100 of PAGESEL (13h).
10.5.1 PTP Control Register (PTP_CTL), Page 4
This register provides basic control of the PTP 1588 operation.
Table 10-39. PTP Control Register (PTP_CTL), address 0x14
Bit Bit Name Default Description
15:1 RESERVED 000, RO Reserved: Writes ignored, Read as 0
3
12:1 TRIG_SEL 000, RW PTP Trigger Select:
0 This field selects the Trigger for loading control information or for enabling the
Trigger.
9 TRIG_DIS 0, RW/SC Disable PTP Trigger:
Setting this bit will disable the selected Trigger. This bit does not indicate Disable
status for Triggers. The PTP Trigger Status Register should be used to determine
Trigger Status. This bit is self-clearing and will always read back as 0.
Disabling a Trigger will not disconnect it from a GPIO pin. The Trigger value will still
be driven to the GPIO if the Trigger is assigned to a GPIO.
8 TRIG_EN 0, RW/SC Enable PTP Trigger:
Setting this bit will enable the selected Trigger. This bit does not indicate Enable
status for Triggers. The PTP Trigger Status Register should be used to determine
Trigger Status. This bit is self-clearing and will always read back as 0.
7 TRIG_READ 0, RW/SC Read PTP Trigger:
Setting this bit will begin the Trigger Read process. The Trigger is selected based on
the setting of the TRIG_SEL bits in this register. Upon setting this bit, subsequent
reads of the PTP_TDR will return the Trigger Control values. Fields are read in the
same order as written.
6 TRIG_LOAD 0, RW/SC Load PTP Trigger:
Setting this bit will disable the selected Trigger and begin the Trigger load process.
The Trigger is selected based on the setting of the TRIG_SEL bits in this register.
Upon setting this bit, subsequent writes to the PTP_TDR will set the Trigger Control
fields for the selected Trigger. The Trigger Load is completed once all fields have
been written, or the TRIG_EN bit has been set in this register. This bit is self-
clearing and will read back as 0 when the Trigger Load is completed either by
writing all Trigger Control fields, or by setting the Trigger Enable.
5 PTP_RD_CLK 0, RW/SC Read PTP Clock:
Setting this bit will cause the device to sample the PTP Clock time value. The time
value will be made available for reading through the PTP_TDR register. This bit is
self-clearing and will always read back as 0.
4 PTP_LOAD_CLK 0, RW/SC Load PTP Clock:
Setting this bit will cause the device to load the PTP Clock time value from data
previously written to the PTP_TDR register. This bit is self-clearing and will always
read back as 0.
3 PTP_STEP_CLK 0, RW/SC Step PTP Clock:
Setting this bit will cause the device to add a value to the PTP Clock. The value to
be added is the value previously written to the PTP_TDR register. This bit is
selfclearing and will always read back as 0.
2 PTP_ENABLE 0, RW Enable PTP Clock:
Setting this bit will enable the PTP Clock. Reading this bit will return the current
enabled value. Writing a 0 to this bit will have no effect.
1 PTP_DISABLE 0, RW/SC Disable PTP Clock:
Setting this bit will disable the PTP Clock. Writing a 0 to this bit will have no effect.
This bit is self-clearing and will always read back as 0.
0 PTP_RESET 0, RW Reset PTP Clock:
Setting this bit will reset the PTP Clock and associated logic. In addition, the 1588
registers will be reset, with the exception of the PTP_COC and PTP_CLKSRC
registers. Unlike other bits in this register, this bit is not self-clearing and must be
written to 0 to release the clock and logic from reset.
112 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83640