Datasheet

DP83640
SNOSAY8E –SEPTEMBER 2007–REVISED APRIL 2013 www.ti.com
Table 10-34. Variance Control Register (VAR_CTRL), address 0x1A
Bit Bit Name Default Description
15 VAR_RDY 0, RO Variance Data Ready Status:
Indicates new data is available in the Variance data register. This bit will be
automatically cleared after two consecutive reads of VAR_DATA.
14:4 RESERVED 000 0000 0000, RO RESERVED: Writes ignored, read as 0.
3 VAR_FREEZE 0, RW Freeze Variance Registers:
Freeze VAR_DATA register.
This bit is ensures that VAR_DATA register is frozen for software reads. This bit is
automatically cleared after two consecutive reads of VAR_DATA.
2:1 VAR_TIMER 00, RW Variance Computation Timer (in ms):
Selects the Variance computation timer period. After a new value is written,
computation is automatically restarted. New variance register values are loaded
after the timer elapses.
Var_Timer = 0 => 2 ms timer (default)
Var_Timer = 1 => 4 ms timer
Var_Timer = 2 => 6 ms timer
Var_Timer = 3 => 8 ms timer
Time units are actually 2
17
cycles of an 8 ns clock, or 1.048576 ms.
0 VAR_ENABLE 0, RW Variance Enable:
Enable Variance computation. Off by default.
10.4.8 Variance Data Register (VAR_DATA), Page 2
This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is
asserted in the VAR_CTRL register. Upon detection of VAR_RDY asserted, software should set the
VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA
register. Since the Variance Data value is 32-bits, two reads of this register are required to get the full
value.
Table 10-35. Variance Data Register (VAR_DATA), address 0x1B
Bit Bit Name Default Description
15:0 VAR_DATA 0000 0000 0000 Variance Data:
0000, RO
Two reads are required to return the full 32-bit Variance Sum value. Following
setting the VAR_FREEZE control, the first read of this register will return the low 16
bits of the Variance data. A second read will return the high 16 bits of Variance data.
10.4.9 Link Quality Monitor Register (LQMR), Page 2
This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides
a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an
interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register,
while the LQDR register controls read/write access to threshold values and current parameter values.
Reading the LQMR register clears warning bits and re-arms the interrupt generation. In addition, this
register provides a mechanims for allowing automatic reset of the 100 Mb link based on the Link Quality
Monitor status.
Table 10-36. Link Quality Monitor Register (LQMR), address 0x1D
Bit Bit Name Default Description
15 LQM_ENABLE 0, RW Link Quality Monitor Enable:
Enables the Link Quality Monitor. The enable is qualified by having a valid 100 Mb
link. In addition, the individual thresholds can be disabled by setting to the
maximum or minimum values.
108 Register Block Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83640