Datasheet

DP83630

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SNLS335B –OCTOBER 2010–REVISED APRIL 2013

10.2.9 PHY Control Register 2 (PHYCR2)

This register provides additional general control.

Table 10-24. PHY Control Register 2 (PHYCR2), address 0x1C

Bit Bit Name Default Description

15:14 RESERVED 00, RO RESERVED: Writes ignored, read as 0.

13 SYNC_ENET EN 0, RW Synchronous Ethernet Enable:

When this bit is 1 and the device is in 100 Mb/s mode, and the MAC

interface is either MII or RMII Master, enables fully synchronous

communication relative to the recovered receive clock. The transmitter is

synchronized to the receiver.

When this bit is 0 or the device settings do not match the above

conditions, the transmitter is synchronous to the local reference clock.

12 CLK_OUT RXCLK 0, RW Enable RX_CLK on CLK_OUT:

When this bit is 1 and the device is in 100 Mb/s mode, the 25 MHz

recovered receive clock (RX_CLK) is driven on CLK_OUT in addition to

RX_CLK. When this bit is 0 or the device is in 10 Mb/s mode, CLK_OUT

reflects the Reference clock.

11 BC_WRITE 0, RW Broadcast Write Enable:

1 = Enables the Serial Management Interface to accept register writes to

PHY Address of 0x1F independent of the local PHY Address value.

0 = Normal operation

10 PHYTER_COMP 0, RW Phyter Compatibility Mode:

1 = Enables Phyter (DP83848) Compatible pinout. Reorders the RX MII

pins and Autonegotiation straps to match the DP83848. Also enables the

CLK_OUT output.

0 = Normal operation

9 SOFT_RESET 0, RW/SC Soft Reset:

Resets the entire device minus the registers - all configuration is

preserved.

1 = Reset, self-clearing.

8:2 RESERVED 0 0000 00, RO RESERVED: Writes ignored, read as 0.

1 CLK_OUT_DIS Strap, RW Disable CLK_OUT Output:

Disables the CLK_OUT output pin.

0 RESERVED 0, RW RESERVED: Must be zero.

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