Datasheet

DP83630

SNLS335B –OCTOBER 2010–REVISED APRIL 2013

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Table 10-21. PHY Control Register (PHYCR), address 0x19 (continued)

Bit Bit Name Default Description

6 LED_CNFG[1] 0, RW LED Configuration

5 LED_CNFG[0] Strap, RW

LED_CNFG[1] LED_CNFG[0] Mode Description

Don't care 1 Mode 1

0 0 Mode 2

1 0 Mode 3

In Mode 1, LEDs are configured as follows:

LED_LINK = ON for Good Link, OFF for No Link

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT = ON for Activity, OFF for No Activity

In Mode 2, LEDs are configured as follows:

LED_LINK = ON for Good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT = ON for Collision, OFF for No Collision

In Mode 3, LEDs are configured as follows:

LED_LINK = ON for Good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT = ON for Full Duplex, OFF for Half Duplex

4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.

Note: The local PHY address cannot be changed via a broadcast write - writing to

PHY address 0x1F register 0x19 will not change the PHYADDR bits.

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