Datasheet

DP83630

SNLS335B –OCTOBER 2010–REVISED APRIL 2013

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10.1.11 MII Interrupt Control Register (MICR)

This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation

include: Link Quality Monitor, Energy Detect State Change, Link State Change, Speed Status Change,

Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full. The

individual interrupt events must be enabled by setting bits in the MII Interrupt Status and Event Control

Table 10-13. MII Interrupt Control Register (MICR), address 0x11

Bit Bit Name Default Description

15:4 RESERVED 0000 0000 0000, RO RESERVED: Writes ignored, read as 0.

3 PTP_INT_SEL 0, RW PTP Interrupt Select:

Maps PTP Interrupt to the MISR register in place of the Duplex Interrupt. The

Duplex Interrupt will be combined with the Speed Interrupt.

1 = Map PTP Interrupt to MISR[11] , Speed/Duplex Interrupt to MISR[12]

0 = Map Duplex Interrupt to MISR[11], Speed Interrupt to MISR[12]

2 TINT 0, RW Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will

continue to be generated as long as this bit remains set.

1 = Generate an interrupt.

0 = Do not generate interrupt.

1 INTEN 0, RW Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR register.

1 = Enable event based interrupts.

0 = Disable event based interrupts.

0 INT_OE 0, RW Interrupt Output Enable:

Enable interrupt events to signal via the PWRDOWN/INTN pin by configuring the

PWRDOWN/INTN pin as an output.

1 = PWRDOWN/INTN is an Interrupt Output.

0 = PWRDOWN/INTN is a Power Down Input.

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