Datasheet

DP83630
www.ti.com SNLS335B –OCTOBER 2010–REVISED APRIL 2013
10.1 REGISTER DEFINITION
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW = Read Write access
— SC = Register sets on event occurrence and Self-Clears when event ends
— RW/SC = ReadWrite access/Self Clearing bit
— RO = Read Only access
— COR = Clear On Read
— RO/COR = Read Only, Clear On Read
— RO/P = Read Only, Permanently set to a default value
— LL = Latched Low and held until read, based upon the occurrence of the corresponding event
— LH = Latched High and held until read, based upon the occurrence of the corresponding event
10.1.1 Basic Mode Control Register (BMCR)
Table 10-3. Basic Mode Control Register (BMCR), address 0x00
Bit Bit Name Default Description
15 RESET 0, RW/SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is complete.
The configuration is re-strapped.
14 LOOPBACK 0, RW Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive data
path.
Setting this bit may cause the descrambler to lose synchronization and produce a 500
µs “dead time” before any valid data will appear at the MII receive outputs.
13 SPEED SELECTION Strap, RW Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100 Mb/s.
0 = 10 Mb/s.
12 AUTO-NEGOTIATION Strap, RW Auto-Negotiation Enable:
ENABLE
Strap controls initial value at reset.
If FX is enabled (FX_EN = 1), then this bit will be reset to 0.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is
set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
11 POWER DOWN 0, RW Power Down:
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is enabled during a power
down condition. This bit is ORd with the input from the PWRDOWN_INT pin. When the
active low PWRDOWN_INT pin is asserted, this bit will be set.
10 ISOLATE 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
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