Datasheet

DP83630

www.ti.com

SNLS335B –OCTOBER 2010–REVISED APRIL 2013

7.2.9 Code-Group Alignment

The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the

descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5

bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group

pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.

7.2.10 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B

nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and

replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble

pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the

duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair

denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

7.2.11 100BASE-TX Link Integrity Monitor

The 100BASE-TX link monitor ensures that a valid and stable link is established before enabling both the

Transmit and Receive PCS layer.

Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state and enable the

transmit and receive functions.

7.2.12 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle

code-groups which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83630 will assert RX_ER and present RXD[3:0] = 1110 to the MII for

the cycles that correspond to received 5B code-groups until at least two IDLE code-groups are detected.

In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.

Once at least two IDLE code-groups are detected, RX_ER and CRS become de-asserted.

7.3 100BASE-FX OPERATION

The DP83630 provides IEEE 802.3 compliant 100BASE-FX operation. Configuration of FX mode is via

strap option, or through the register interface.

7.3.1 100BASE-FX Transmit

In 100BASE-FX mode, the device Transmit pins connect to an industry standard Fiber Transceiver with

PECL signaling through a capacitively coupled circuit.

In FX mode, the device bypasses the Scrambler and the MLT3 encoder. This allows for the transmission

of serialized 5B4B encoded NRZI data at 125 MHz.

The only added functionality from 100BASE-TX is the support for Far-End Fault data generation.

7.3.2 100BASE-FX Receive

In 100BASE-FX mode, the device Receive pins connect to an industry standard Fiber Transceiver with

PECL signaling through a capacitively coupled circuit.

In FX mode, the device bypasses the MLT3 Decoder and the Descrambler. This allows for the reception of

serialized 5B4B encoded NRZI data at 125 MHz.

The only added functionality for 100BASE-FX from 100BASE-TX is the support of Far-End Fault detection.

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